Z16C32 Datasheet, PDF(22/121 Page) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

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Z16C32 Datasheet, PDF (22/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

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ZILOG

PRELIMINARY

Z16C32 IUSCâ¢

This section describes the function of the various bits in the

registers of the device. Throughout this section the follow-

ing conventions are discussed:

Control bits are written and read by the CPU and are not

modified by the device. Command bits are written by the

CPU to initiate an action in the device and are read as

zeros. Status bits are controlled by the device and are read

to check device status. Any writes to status bits are ignored

by the device. Command/Status bits are controlled by both

the device and the CPU. They may be written and read by

the CPU and may also be modified by the device.

Reserved bits are not used in this implementation of the

device and may or may not be physically present in the

device. Any reserved bits that are physically present are

readable and writable, but reserved bits that are not

present are always read as zeros. To ensure compatibility

with future versions of the device, reserved bits should

always be written with zeros. Reserved commands should

not be used for the same reason.

First, the DMA registers unique to the IUSC are described

in the following pages (Figures 7-16) and then the serial

channel registers are described (Figures 17-80).

Address: 00000 (Shared) *

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 Tx Channel

0 0 1 Rx Channel

0 1 0 Reserved

0 1 1 Reserved

1 0 0 Reserved

1 0 1 Reserved

1 1 0 Reserved

1 1 1 Reserved

Channel Select (WO)**

0 0 0 0 Null Command

0 0 0 1 Reset This Channel

0 0 1 0 Start This Channel

0 0 1 1 Start/Continue This Channel

0 1 0 0 Pause This Channel

0 1 0 1 Abort This Channel

0 1 1 0 Reserved

0 1 1 1 Start/Init This Channel

1 0 0 0 Reset Highest IUS

1 0 0 1 Reset All Channels

1 0 1 0 Start All Channels

1 0 1 1 Start/Continue All Channels

1 1 0 0 Pause All Channels

1 1 0 1 Abort All Channels

1 1 1 0 Reserved

1 1 1 1 Start/Init All Channels

Channel Command

Notes:

* (Shared) means, shared between DMA Channels

** (WO) means Write Only

Upper//Lower Byte Select (WO)

Address 0 (WO)

Address 1 (WO)

Address 2 (WO)

Address 3 (WO)

Address 4 (WO)

Byte//Word Access (WO)

Pointer Channel Select (WO)

Master Bus Request Enable

Figure 7. DMA Command/Address Register

PS97USC0200

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