Z16C32 Datasheet, PDF (88/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Address: None _*
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
0 0 0 8 Bits
0 0 1 1 Bit
0 1 0 2 Bits
0 1 1 3 Bits
1 0 0 4 Bits
1 0 1 5 Bits
1 1 0 6 Bits
1 1 1 7 Bits
* Refer to Figure 22 (Channel Control Register)
Bits15-14 for Access Method
Reserved
HDLC Tx Last
Character Length
Reserved
Tx Submode 0
Tx Submode 1
Tx Submode 2
Tx Submode 3
Figure 79. Transmit Status Block Register (TSBR)
Address: none
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Shift Right Address
/INT Open-Drain
16-Bit Bus
/BUSREQ Type
00
01
10
11
Status Acknowledge
Single Pulse Acknowledge
Reserved
Double Pulse Acknowledge
INTACK Mode
* Must be programmed as 0.
0*
Tri-State All Pins
Separate Address for 8-Bit Bus
Figure 80. Bus Configuration Register (BCR)
88
PS97USC0200