Z16C32 Datasheet, PDF (56/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Address: 00011
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
Reserved
Wait for Rx DMA Trigger
0 0 No Status Block
0 1 One Word Status Block
1 0 Two Word Status Block
1 1 Reserved
Rx Status
Block Transfer
0 0 All Zeros
0 1 All Ones
1 0 Alternating 1 and 0
1 1 Alternating 0 and 1
Tx Preamble
Pattern
0 0 8 Bits
0 1 16 Bits
1 0 32 Bits
1 1 64 Bits
Tx Preamble
Length
Tx Shaved Bit Length
(Async Only)
(All Sync)
Tx Flag Preamble
Wait for Tx DMA Trigger
0 0 No Status Block
0 1 One Word Status Block
1 0 Two Word Status Block
1 1 Reserved
Tx Control
Block Transfer
Figure 49. Channel Control Register (CCR)
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PS97USC0200