Z16C32 Datasheet, PDF (68/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Address: 01111
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
0 0 Disabled
0 1 Rising Edge Only
1 0 Falling Edge Only
1 1 Both Edges
BRG0 ZC IA
BRG1 ZC IA
DPLL SYNC IA
RCC Overflow IA
/CTS
Interrupt
Arm
0 0 Disabled
0 1 Rising Edge Only
1 0 Falling Edge Only
1 1 Both Edges
/DCD
Interrupt
Arm
0 0 Disabled
0 1 Rising Edge Only
1 0 Falling Edge Only
1 1 Both Edges
/TxREQ
Interrupt
Arm
0 0 Disabled
0 1 Rising Edge Only
1 0 Falling Edge Only
1 1 Both Edges
/RxREQ
Interrupt
Arm
0 0 Disabled
0 1 Rising Edge Only
1 0 Falling Edge Only
1 1 Both Edges
/TxC
Interrupt
Arm
0 0 Disabled
0 1 Rising Edge Only
1 0 Falling Edge Only
1 1 Both Edges
/RxC
Interrupt
Arm
Figure 61. Status Interrupt Control Register (SICR)
68
PS97USC0200