Z16C32 Datasheet, PDF (7/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Z16C32 IUSC^™
/RD Read Strobe (input/tri-state output, active Low). This
line indicates a read cycle on the bus, for host processors/
buses having this kind of signalling. It is an output when the
IUSC has taken control of the bus and is operating in
master mode, otherwise, it is an input that is qualified by
/CS Low or /INTACK Low. For master read cycles, the IUSC
captures data at the rising (trailing) edge of this line. For
slave read cycles the IUSC provides valid data on the AD
lines within the specified access time after this line goes
Low, and keeps the data valid until after the master
releases this line to High.
/WR Write Strobe (input/tri-state output, active Low). This
line indicates write cycles on the bus, for host processors/
buses having this kind of signalling. It is an output when the
IUSC has taken control of the bus and is operating in
master mode, otherwise it is an input that is qualified by
/CS Low. For slave write cycles, the IUSC captures write
data at the rising (trailing) edge of this line. For master write
cycles, the IUSC places valid data on the AD lines before
it drives this signal to Low , and keeps the data valid until
after it drives this line back to High.
B//W Byte / Word Select (tri-state output, High indicates
8-bit transfer). When the IUSC takes control of the bus and
operates as a master, a High on this line indicates that a
byte is to be transferred, and a Low indicates that 16 bits
are to be transferred. The IUSC ignores this signal during
slave cycles: it takes the byte/word distinction from an AD
line at the rising edge of /AS, or from a bit in the serial or
DMA Command/Address Register.
/WAIT//RDY Wait, Ready, or Acknowledge handshaking
(input/tri-state output, active Low). This line is an input
when the IUSC has taken control of the bus and is operat-
ing in master mode. For slave cycles, the IUSC activates
this line as an output. In both directions, the line can carry
wait or acknowledge signalling depending on the state of
the S//D input during the initial BCR write. If S//D is High
when the BCR is written, this line operates as a Ready/Wait
line for Zilog and most Intel processors. In this mode, the
IUSC will not complete a master cycle while this line is Low,
and it asserts this line Low until it’s ready to complete an
interrupt acknowledge cycle; it never asserts this line when
the host accesses one of the IUSC registers.
If S//D is Low when the BCR is written, this line operates
thereafter as an Acknowledge line for Motorola and some
Intel processors. In this mode, the IUSC will not complete
a master cycle until this line is Low. It asserts this line Low
for register read and write cycles, and when it is ready to
complete an interrupt acknowledge cycle.
For slave cycles, this is a full time (totem pole) output. The
board designer can combine this signal with similar sig-
nals from other slaves, by means of an external logic gate
or a tri-state or open-collector driver.
/INT Interrupt Request (output, active Low). The IUSC
drives this line Low when (1) its IEI pin is High, (2) one or
more of its interrupt condition(s) is (are) enabled and
pending, and (3) the Under Service flag is not set for its
highest priority enabled/pending condition, nor for any
higher-priority internal condition. Software can program
whether the bus interface drives this pin in a totem-pole or
an open-drain fashion.
/INTACK Interrupt Acknowledge (input, active Low). A
Low on this line indicates that the host processor is
performing an interrupt acknowledge cycle. In some sys-
tems, a Low on this line may further indicate that external
logic has selected this IUSC as the device to be acknowl-
edged, or as a potential device to be acknowledged. A
field in the Bus Configuration Register selects whether this
line carries a level-sensitive “status” signal that the IUSC
should sample at the leading edge of /AS or /DS, or a
single-pulse or double-pulse protocol. The IUSC responds
to an interrupt acknowledge cycle in a variety of ways
depending on this programming and the state of the /INT
and IEI lines, as described in the text.
IEI Interrupt Enable In (input, active High). This signal and
the IEO pin can be part of an interrupt-acknowledge daisy
chain with other devices that may request interrupts. If IEI
is High outside of an interrupt acknowledge cycle, one or
more IUSC interrupt condition(s) is (are) enabled and
pending, and the Under Service flag isn’t set for the highest
priority condition nor for any higher-priority one, then the
IUSC requests an interrupt by driving its /INT pin Low. If the
IEI pin is High during an interrupt acknowledge cycle, one
or more IUSC interrupt condition(s) is (are) enabled and
pending, and the Under Service flag isn’t set for the highest
priority condition nor for any higher-priority, then the IUSC
keeps IEO Low and responds to the cycle.
IEO Interrupt Enable Out (output, active High). This signal
and/or IEI can be part of an interrupt acknowledge daisy
chain with other devices that may request interrupts. The
IUSC drives its IEO pin Low whenever its IEI pin is Low,
and/or if the Under Service flag is set for any condition. This
IUSC drives this signal slightly differently during an inter-
rupt acknowledge cycle, in that it also forces IEO Low if it
is (has been) requesting an interrupt.
PS97USC0200
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