Z16C32 Datasheet, PDF (48/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Address: 00001
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
0 0 0 0 Asynchronous
0 0 0 1 External Synchronous
0 0 1 0 Isochronous
0 0 1 1 Asynchronous with CV
0 1 0 0 Monosync
0 1 0 1 Bisync
0 1 1 0 HDLC
0 1 1 1 Transparent Bisync
1 0 0 0 NBIP
1 0 0 1 802.3
1 0 1 0 Reserved
1 0 1 1 Reserved
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
Rx Submode 0
Rx Submode 1
Rx Submode 2
Rx Submode 3
0 0 0 0 Asynchronous
0 0 0 1 Reserved
0 0 1 0 Isochronous
0 0 1 1 Asynchronous with CV
0 1 0 0 Monosync
0 1 0 1 Bisync
0 1 1 0 HDLC
0 1 1 1 Transparent Bisync
1 0 0 0 NBIP
1 0 0 1 802.3
1 0 1 0 Reserved
1 0 1 1 Reserved
1 1 0 0 Slaved Monosync
1 1 0 1 Reserved
1 1 1 0 HDLC Loop
1 1 1 1 Reserved
Transmitter
Mode
Tx Submode 0
Tx Submode 1
Tx Submode 2
Tx Submode 3
Figure 35. Channel Mode Register (CMR)
Receiver
Mode
48
PS97USC0200