Z16C32 Datasheet, PDF (12/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Z16C32 IUSC^™
DMA AND BUS INTERFACE CAPABILITIES (Continued)
There are six sources of Receive Status interrupt. Each one
is individually armed: Receiver exited hunt, received idle
line, received break/abort, received code violation/end-of-
transmission/end-of-message, parity error/abort and over-
run error. The Receive Data interrupt is generated when-
ever the receive FIFO fills with data beyond the level
programmed in the Receive Interrupt Control Register
(RICR). There are six sources of Transmit Status interrupt.
Each one is individually armed: Preamble sent, idle line
sent, abort sent, end-of-frame/end-of-message sent, CRC
sent and underrun error. The Transmit Data interrupt is
generated whenever the transmit FIFO empties below the
level programmed in the Transmit Interrupt Control Regis-
ter (TICR).
The I/O Status interrupt serves to report transitions on any
of six pins. Interrupts are generated on either or both
edges with individual edge selection and arming for each
pin. The pins that can be programmed to generate I/O
Status interrupts are /RxC, /TxC, /RxREQ, /TxREQ, /DCD
and /CTS. These interrupts are independent of the pro-
grammed function of the pins.
The Device Status interrupt has four individually enabled
sources: Receive character counter underflow, DPLL sync
acquired, BRG1 zero count and BRGO zero count. Refer
to the IUSC Technical Manual for more details.
COMMUNICATION BETWEEN THE DMA AND SERIAL CHANNELS
The IUSC’s intra-chip communication between the DMA
and serial communications controller gives it the power to
achieve higher efficiency than is possible with a separate
DMA controller. The Linked Frame Status Transfer feature
writes the status and byte count of each received frame to
memory as part of an array or linked list. This provides a
simple and easy to use mechanism for storing the results
of a received message without arbitrary restrictions on how
quickly the host software must examine the results. Simi-
larly, control information for transmit frames can be auto-
matically read by the DMA from the array or link and
transferred into registers in the serial logic.
In all modes, the DMA can accept a signal from the serial
channel for early buffer termination. When the end of a
message is received, the data is transferred to the buffer
and the status is written to memory. The status is written
after the data in single buffer and pipelined modes or to the
array/link in array and linked-list modes if Linked-Frame
Status Transfer is enabled. This early buffer termination is
treated identically to the terminal count condition in the
DMA. Therefore, the receipt of the end of a message is a
seamless transition from one memory buffer to the next.
An example of using these intercommunication features
using linked list mode is shown in Figure 4. This example
shows the format of a ring of memory buffers with the linked
frame status transfer and ring buffer features enabled. Any
protocol that sets the “RxBound” bit (RCSR4 = 1), like
HDLC or 802.3, is appropriate to this example. The linked
list is shown in Figure 4 with three links for simplicity and
may be as large as memory allows. The sixth word in each
list entry is reserved and should not be used (it keeps the
list entries on 32-bit boundaries). If the end of the buffer is
reached and it is not the end of the frame, the IUSC writes
zeros as the status and count. Also, if the transmit channel
needs to start a new memory buffer other than at the
beginning of a frame, the DMA ignores the transmit control
block.
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PS97USC0200