Z16C32 Datasheet, PDF (21/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
S//D
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D//C
0
X
0
X
X
X
X
X
X
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
PRELIMINARY
Z16C32 IUSC^™
Table 1. Register Address List (Continued)
Address
A5-A1
Name
Description
XXXXX
00000
00001
00011
00100
BCR
DCAR
TDCMR
DCR
DACR
Bus Configuration Register
DMA Command/Address Register
Transmit DMA Channel Mode Register
DMA Control Register
DMA Array Count Register
01001
01010
01100
01101
01110
BDCR
DIVR
DICR
CDIR
SDIR
Burst Dwell Control Register
DMA Interrupt Vector Register
DMA Interrupt Control Register
Clear DMA Interrupt Register
Set DMA Interrupt Register
01111
10101
10110
10111
11101
TDIAR
TBCR
TARL
TARU
NTBCR
Transmit DMA Interrupt Arm
Transmit Byte Count Register
Transmit Address Register (Lower)
Transmit Address Register (Upper)
Next Transmit Byte Count Register
11110
11111
00001
01111
10101
NTARL
NTARU
RDMR
RDIAR
RBCR
Next Transmit Address Register (Lower)
Next Transmit Address Register (Upper)
Receive DMA Mode Register
Receive DMA Interrupt Arm
Receive DMA Byte Count Register
10110
10111
11101
11110
11111
RARL
RARU
NRBCR
NRARL
NRARU
Receive Address Register (Lower)
Receive Address Register (Upper)
Next Receive Byte Count Register
Next Receive Address Register (Lower)
Next Receive Address Register (Upper)
PS97USC0200
21