Z16C32 Datasheet, PDF (80/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Address: 11010
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
Tx Buffer Empty (RO)
Tx Underrun
All Sent (RO)
Tx CRC Sent
Tx EOF/EOT Sent
Tx Abort Sent
Tx Idle Sent
Tx Preamble Sent
0 0 0 SYNC/Flag/Normal
0 0 1 Alternating 1 and 0
0 1 0 All Zeros
0 1 1 All Ones
1 0 0 Reserved
1 0 1 Alternating Mark and Space
1 1 0 Space
1 1 1 Mark
Tx Idle Line
Condition
Reserved
0 0 0 0 Null Command
0 0 0 1 Reserved
0 0 1 0 Preset CRC
0 0 1 1 Reserved
0 1 0 0 Select Timeslot Assignment
0 1 0 1 Select FIFO Status
0 1 1 0 Select Interrupt Level
0 1 1 1 Select Request Level
1 0 0 0 Send Frame/Message
1 0 0 1 Send Abort
1 0 1 0 Reserved
1 0 1 1 Reserved
1 1 0 0 Reset DLE Inhibit
1 1 0 1 Set DLE Inhibit
1 1 1 0 Reset EOF/EOM
1 1 1 1 Set EOF/EOM
Transmit
Command (WO)
Figure 72. Transmit Command/Status Register (TCSR)
80
PS97USC0200