Z16C32 Datasheet, PDF(31/121 Page) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

Z16C32 Datasheet, PDF (31/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

◁

ZILOG

PRELIMINARY

Address: 01101 (Shared)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Z16C32 IUSCâ¢

Reset Tx IP (WO)

Reset Rx IP (WO)

Reserved

Reset Tx IUS (WO)

Reset Rx IUS (WO)

Reserved

Figure 17. Clear DMA Interrupt Register (CDIR)

Address: 01110 (Shared)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Set Tx IP

Set Rx IP

Reserved

Set Tx IUS

Set Rx IUS

Reserved

Figure 18. Set DMA Interrupt Register (SDIR)

Address: 01111 *

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Software Abort IA

Hardware Abort IA

Buffer Termination IA

Array Termination IA

Reserved

Figure 19. Tx/Rx DMA Interrupt Arm (TDIAR)/(RDIAR)

Notes:

* The format of this register is the same for the receiver and transmitter. The transmit register

is accessed by addressing it with the D//C pin Low (0). The receive register is accessed by

addressing it with the D//C pin High (1). This applies to Figures 19 through 25.

PS97USC0200

▷