Z16C32 Datasheet, PDF (60/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Address: 00111
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
0 0 0 0 0 Null Address
0 0 0 0 1 High Byte of Shifters
0 0 0 1 0 CRC Byte 0
0 0 0 1 1 CRC Byte 1
0 0 1 0 0 Rx FIFO (Write)
0 0 1 0 1 Clock Multiplexer Outputs
0 0 1 1 0 CTR0 and CTR1 Counters
0 0 1 1 1 Clock Multiplexer Inputs
0 1 0 0 0 DPLL State
0 1 0 0 1 Low Byte of Shifters
0 1 0 1 0 CRC Byte 2
0 1 0 1 1 CRC Byte 3
0 1 1 0 0 Tx FIFO (Read)
0 1 1 0 1 Reserved
0 1 1 1 0 I/O and Device Status Latches
0 1 1 1 1 Internal Daisy Chain
1 0 0 0 0 Reserved
1 0 0 0 1 Reserved
1 0 0 1 0 Reserved
1 0 0 1 1 Reserved
1 0 1 0 0 Reserved
1 0 1 0 1 Reserved
1 0 1 1 0 Rx Count Holding Register
1 0 1 1 1 Reserved
1 1 0 0 0 Reserved
1 1 0 0 1 Reserved
1 1 0 1 0 Reserved
1 1 0 1 1 4453H
1 1 1 0 0 Reserved
1 1 1 0 1 Reserved
1 1 1 1 0 Reserved
1 1 1 1 1 4453H
Reserved
Figure 53. Test Mode Control Register (TMCR)
Test
Register
Address
Note:
When software writes the value 1F to the LS byte of the Test Mode Control Register (TMCR),
and then reads the Test Mode Data Register (TMDR), current versions of the Z16C32 will return
hex 4453. Future revisions, if any, will return other values.
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PS97USC0200