Z16C32 Datasheet, PDF (38/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Base Address
Base Address + 1
Base Address + 2
Base Address + 3
Base Address + 4
Base Address + 5
Base Address + 6
Base Address + 7
Base Address + 8
Base Address + 9
Base Address + 10
Base Address + 11
AD7
AD0
Buffer #1
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
CNT<15-8>
Buffer #2
CNT<7-0>
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
CNT<15-8>
CNT<7-0>
Z16C32 IUSC^™
Last Base Address
Last Base Address + 1
Last Base Address + 2
Last Base Address + 3
Last Base Address + 4
Last Base Address + 5
Base Address Register
After Termination
Dummy
Ignored
Ignored
Ignored
Ignored
00000000
00000000
Figure 28a. Array-Chained, 8-Bit Bus, Big End Array
Note:
The addition of frame status/control information in the array with Linked Frame
Status Transfer Enabled is similar for Big and Little End Array. See Figure 28b.
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PS97USC0200