Z16C32 Datasheet, PDF (36/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Base Address
Base Address + 2
Base Address + 4
Base Address + 6
Base Address + 8
Base Address + 10
Base Address + 12
Base Address + 14
Base Address + 16
Base Address + 18
Base Address + 20
Base Address + 22
Base Address + 24
Base Address + 26
Base Address + 28
Base Address + 30
Base Address + 32
Base Address + 34
AD15
AD0
Buffer #1
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
CNT <15-8>
CNT <7-0>
RSB/TCB <15-8> RSB/TCB <7-0>
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
0
0
Buffer #2
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
CNT <15-8 >
CNT <7-0>
RSB/TCB <15-8> RSB/TCB <7-0>
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
0
0
Buffer #3
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
CNT <15-8>
CNT <7-0>
RSB/TCB <15-8> RSB/TCB <7-0>
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
0
0
Last Base Address
Last Base Address + 2
Last Base Address + 4
Base Address Register
After Termination
Dummy
Ignored
Ignored
00000000
Ignored
Ignored
00000000
Figure 26b. Array-Chained, 16-Bit Bus, Big End Array
Linked Frame Status Transfer Enabled
Z16C32 IUSC^™
36
PS97USC0200