Z16C32 Datasheet, PDF (82/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Address: 11011
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
0 0 0 0 No Slot (Disabled)
0 0 0 1 1 Slot
0 0 1 0 2 Slots
0 0 1 1 3 Slots
0 1 0 0 4 Slots
0 1 0 1 5 Slots
0 1 1 0 6 Slots
0 1 1 1 7 Slots
1 0 0 0 8 Slots
1 0 0 1 9 Slots
1 0 1 0 10 Slots
1 0 1 1 11 Slots
1 1 0 0 12 Slots
1 1 0 1 13 Slots
1 1 1 0 14 Slots
1 1 1 1 15 Slots
0 0 0 No Offset
0 0 1 7 Clocks Offset
0 1 0 6 Clocks Offset
0 1 1 5 Clocks Offset
1 0 0 4 Clocks Offset
1 0 1 3 Clocks Offset
1 1 0 2 Clocks Offset
1 1 1 1 Clock Offset
Slot Offset
(WO)
Concatenated
Slots (WO)
TC1R Read Count/TC
Tx Underrun IA
Wait for Send Command
Tx CRC Sent IA
Tx EOF/EOT Sent IA
Tx Abort Sent IA
Tx Idle Sent IA
Tx Preamble Sent IA
1 (WO)
Figure 73c. Transmit Interrupt Control Register (TICR)
82
PS97USC0200