Z16C32 Datasheet, PDF (35/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Base Address
Base Address + 2
Base Address + 4
Base Address + 6
Base Address + 8
Base Address + 10
Base Address + 12
Base Address + 14
Base Address + 16
AD15
Buffer #1
AD<31-24>
AD<15-8>
Buffer #2
CNT<15-8>
AD<31-24>
AD<15-8>
Buffer #3
CNT<15-8>
AD<31-24>
AD<15-8>
CNT<15-8>
AD0
AD<23-16>
AD<7-0>
CNT<7-0>
AD<23-16>
AD<7-0>
CNT<7-0>
AD<23-16>
AD<7-0>
CNT<7-0>
Z16C32 IUSC^™
Last Base Address
Last Base Address + 2
Last Base Address + 4
Base Address Register
After Termination
Dummy
Ignored
Ignored
00000000
Ignored
Ignored
00000000
Figure 26a. Array-Chained, 16-Bit Bus, Big End Array
Note:
The addition of frame status/control information in the array with Linked Frame
Status Transfer Enabled is similar for Big and Little End Array. See Figure 26b.
PS97USC0200
35