Z16C32 Datasheet, PDF (26/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Address: 00011 (Shared)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
00
01
10
11
End of Demand or Burst
End of Demand Only
End of Burst Only
Reserved
00
01
10
11
Tx Channel
Rx Channel
Alternating
Reserved
Channel
Priority
00
01
10
11
32-bit Linear
Reserved
Segmented 16/16
Segmented 8/24
Addressing
Mode
/UAS Every Transaction
One Wait Every Transaction
Enable Transaction Status
Bus Inactive Time
Reserved
Reserved
Reserved
Reserved
DMA Request
Arbitration
Link Array Big End/Little End
Preempt Enable
Figure 11. DMA Control Register (DCR)
26
PS97USC0200