Z16C32 Datasheet, PDF (42/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Base Address
Base Address + 2
Base Address + 4
Base Address + 6
Base Address + 8
Base Address + 10
Buffer #1
AD15
AD0
AD<31-24>
AD<23-16>
AD <15-8>
AD<7-0>
CNT<15-8>
CNT<7-0>
RSB/TCB <15-8> RSB/TCB <7-0>
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
0
0
Base Address + 12
Base Address + 14
#2 Base Address
#2 Base Address + 2
#2 Base Address + 4
#2 Base Address + 6
#2 Base Address + 8
#2 Base Address + 10
Base #2
Buffer #2
AD<31-24>
AD<23-16>
AD <15-8>
AD<7-0>
AD<31-24>
AD<23-16>
AD <15-8>
AD<7-0>
CNT<15-8>
CNT<7-0>
RSB/TCB <15-8> RSB/TCB <7-0>
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
0
0
#2 Base Address + 12
#2 Base Address + 14
#3 Base Address
#3 Base Address + 2
#3 Base Address + 4
#3 Base Address + 6
#3 Base Address + 8
#3 Base Address + 10
Base #3
Buffer #3
AD<31-24>
AD<23-16>
AD <15-8>
AD<7-0>
AD<31-24>
AD<23-16>
AD <15-8>
AD<7-0>
CNT<15-8>
CNT<7-0>
RSB/TCB <15-8> RSB/TCB <7-0>
RCHR/TCLR <15-8> RCHR/TCLR <7-0>
0
0
Figure 30b. Linked Array-Chained, 16-Bit Bus, Big End Array
Z16C32 IUSC^™
42
PS97USC0200