Z16C32 Datasheet, PDF (14/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
DATA COMMUNICATIONS CAPABILITIES
Z16C32 IUSC^™
The IUSC provides a full-duplex channel programmable
for use in any common data communication protocol. The
receiver and transmitter are completely independent and
each is supported by a 32-byte deep FIFO and a 16-bit
frame length counter. All modes allow optional even, odd,
mark or space parity. Synchronous modes allow the choice
of either of two 16-bit or a 32-bit CRC polynomials. Char-
acter length of up to 8 bits can be programmed for the
receiver and transmitter independently. Error and status
conditions are carried with the data in the receive FIFO to
greatly reduce the CPU overhead required to send or
receive a message, while key control parameters accom-
pany transmit characters through the Tx FIFO. Interrupts
can be individually armed to signal such conditions as
overrun, parity error, framing error, end-of-frame, idle line
received, sync acquired, transmit underrun, CRC sent,
closing sync/flag sent, abort sent, idle line sent and pre-
amble sent. In addition, several useful internal signals like
receive character boundary, received sync, transmit char-
acter boundary and transmission complete can be sent to
pins for use by external circuitry.
Protocols
Asynchronous Mode. The receiver and transmitter handle
data at a rate of 1/16, 1/32, or 1/64 the clock rate. The
receiver rejects start bits less than one-half a bit time and
includes recovery logic following a framing error. The
transmitter is capable of sending one, two, or anywhere in
the range of 9/16th to two stop bits per character in 1/16 bit
increments.
Nine-Bit Mode. This mode is identical to async except that
the receiver checks for the status of an additional address/
data bit between the parity bit and the stop bit. The value
of this bit is FIFO’ed along with the data. In the transmitter,
this bit is automatically inserted with the value that is
FIFO’ed from the transmit data.
Isochronous Mode. Both transmitter and receiver oper-
ate on start-stop (async) data using a 1x clock. The
transmitter sends one or two stop bits.
opening and closing flags, performs zero insertion and
can be programmed to send an abort, an extended abort,
a flag or CRC and a flag on transmit underrun. The
transmitter automatically sends a closing flag with optional
CRC at the end of a programmed message length. Shared-
zero flags are selected in the transmitter and a separate
character length is programmed for the last character in
the frame.
Frames terminated with an ABORT can be marked with a
status bit on the preceding character in addition to the
status interrupt that can be enabled. Abort is only detected
in-frame and, therefore, eliminates false detection due to
an idle line. The IUSC provides four choices (flag, all 1s, all
0s, or alternating 1s and 0s) of line preamble to condition
the line before beginning data transmission. This feature is
valuable to get the receiver DPLL in sync and as a flow
control mechanism to slow down frame transmission with-
out slowing down the clock or disabling the transmitter.
HDLC Loop Mode. This mode is available only in the
transmitter and allows the IUSC to be used in an HDLC
Loop configuration. In this mode, the receiver is pro-
grammed to operate in HDLC mode to allow the transmitter
to echo received messages. Upon receipt of a particular
bit pattern (actually a sequence of seven consecutive
ones) the transmitter stops repeating data and inserts its
own frame(s).
802.3 Mode. This mode implements the data format of
IEEE 802.3 with a 16-bit address compare. In this mode,
/DCD and /CTS are used to implement the carrier sense
and collision detect interactions with the receiver and
transmitter. Back-off timing must be provided externally.
Monosync Mode. In this mode, a single character is used
for synchronization. The sync character can be either eight
bits long or the same length as the data characters. The
receiver can automatically strip sync characters from the
received data stream. The transmitter is programmed to
automatically send CRC on either an underrun or at the end
of a programmed message length.
Asynchronous With Code Violations. This is similar to
Isochronous mode except that the start bit is replaced by
a three bit-time code violation pattern as in MIL-STD-
1553B. The transmitter sends zero, one or two stop bits.
HDLC Mode. In this mode, the receiver recognizes flags,
performs optional address matching, accommodates ex-
tended address fields, and performs zero deletion and
CRC checking. The receiver is capable of receiving shared-
zero flags, recognizes abort sequences and can receive
arbitrary length frames. The transmitter automatically sends
Slaved Monosync Mode. This mode is available only in
the transmitter and allows the transmitter (operating just as
though it were in monosync mode) to send data with its
byte boundaries synchronized to those of the received
data.
Bisync Mode. This mode is identical to monosync mode
except that character synchronization requires two suc-
cessive characters. The two characters need not be iden-
tical.
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PS97USC0200