Z16C32 Datasheet, PDF (5/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Z16C32 IUSC^™
/ABORT
/INT
IEI
IEO
GND
VCC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
VCC
/RxREQ
9
10
26
27
1 68
IUSC
61
60
44
43
/BIN
/BUSREQ
CLK
/BOUT
GND
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
GND
VCC
PORT 7
Figure 3. Z16C32 68-Pin PLCC Pin Assignments
PIN DESCRIPTION
Figure 2 shows the logical pin groupings of the IUSC’s
pins, and Figure 3 shows the physical pin assignments.
Only one strobe pin (/DS, /RD, /WR or Pulsed INTACK)
should ever be active at one time. Any unused input pin (if
an input when the IUSC is bus master or slave) must be
pulled up to its inactive state.
/RESET Reset (input, active Low). A Low on this line
places the IUSC in a known, inactive state, and conditions
it so that the data, from the next write operation that asserts
the /CS pin, goes into the Bus Configuration Register
(BCR) regardless of register addressing. /RESET should
be driven Low as soon as possible during power-up, and
as needed when restarting the overall system or the
communications subsystem.
CLK System Clock (input). This signal is the timing refer-
ence for the DMA and bus interface logic. (The serial
controller section is clocked by the selected sources of
receive and transmit clocking.)
AD15-0 Address/Data Bus (inputs/tri-state outputs). After
Reset, these lines carry data between the controlling
microprocessor and the IUSC, and may also carry multi-
plexed addresses of registers within the IUSC. Such op-
eration, between the host processor and the IUSC, is often
called slave mode. Once the software has set up the
device and placed it into operation, these lines also carry
multiplexed addresses and data between the IUSC and
system memory; such operation is called master mode.
AD15-0 can be used in a variety of ways based on whether
the IUSC senses activity on /AS after Reset, and on the
data written to the Bus Configuration Register (BCR).
/CS Chip Select (input, active Low). A Low on this line
indicates that the controlling microprocessor’s current bus
cycle refers to a register in the IUSC. The IUSC ignores /CS
when a Low on /INTACK indicates that the current bus
operation is an interrupt acknowledge cycle. On a multi-
plexed bus the IUSC latches the state of this pin at rising
edges on /AS; on a non-multiplexed bus, it latches /CS at
leading/falling edges on /DS, /RD, or /WR.
PS97USC0200
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