Z16C32 Datasheet, PDF (6/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PIN DESCRIPTION (Continued)
PRELIMINARY
Z16C32 IUSC^™
S//D Serial/DMA (input/tri-state output, input High indi-
cates serial). Cycles with /CS Low, and /INTACK and this
pin both High, access registers in the serial controller
section. Cycles with /INTACK High, and /CS and this pin
both Low, access registers in the DMA controller section.
The state of this line when the Bus Configuration Register
is written determines wait vs acknowledge operation, as
described in the text. On a multiplexed bus, the IUSC
latches the state of this pin at rising edges on /AS; on a non-
multiplexed bus, it latches the state at leading/falling
edges on /DS, /RD, or /WR.
Software can program the IUSC so that when it is acting as
a bus master, it drives this line High to indicate a DMA cycle
for serial data and Low to indicate an “array” or “list”
access. (Array/list accesses read the address and length
of the next memory buffer.)
D//C Data/Control (input/tri-state output, input High indi-
cates Data). A slave read cycle with /CS Low , and all three
of /INTACK, S//D, and this pin High, fetches data from the
serial controller’s receive FIFO through the Receive Data
Register (RDR). A slave write cycle with the same condi-
tions writes data into the transmit FIFO through its Transmit
Data Register (TDR). Slave cycles with /INTACK and S//D
High, and /CS and this pin Low , read or write registers in
the serial controller. On a multiplexed bus, the IUSC
determines which register to access from the low-order AD
lines at the rising edge of /AS; on a non-multiplexed bus it
typically selects the register based on the Least Significant
Bits of the serial controller’s Channel Command/Address
Register. On a multiplexed bus, the IUSC latches the state
of this pin at rising edges on /AS; on a non-multiplexed bus
it latches the state at leading/ falling edges on /DS, /RD, or
/WR.
For slave cycles on a multiplexed bus, with /INTACK High
and both /CS and S//D Low, the state of this line at the rising
edge of /AS selects between the registers of the transmit
DMA channel (Low ) and those of the receive DMA channel
(High). On a non-multiplexed bus, with /INTACK High and
/CS and S//D both Low, the IUSC can take the DMA
channel selection from this line or from the DMA Com-
mand/Address Register.
Software can program the IUSC so that when it is acting as
a bus master, it drives this line High to indicate a DMA cycle
for the receiver and Low to indicate a cycle for the transmit-
ter.
/AS Address Strobe (input/tri-state output, active Low).
After a reset, the IUSC’s bus interface logic monitors this
signal to see if the host bus multiplexes addresses and
data on AD15-0. If the logic sees activity on /AS before (or
during) software writes to the Bus Configuration Register,
then in subsequent slave cycles directed to the IUSC,
it captures register selection from the AD lines, S//D, and
C//D on rising edges of /AS.
When the IUSC takes control of the bus and operates as a
master, it always uses the bus in a multiplexed fashion,
driving /AS Low when it places the least significant 16 bits
of an address on the AD15-0 lines. External devices can be
used to de-multiplex the address and data, if this is
necessary to match the characteristics of the host proces-
sor or host bus.
For a non-multiplexed bus, this pin should be pulled up to
+5V using a resistor of about 10 kOhms. If a processor
uses a non-multiplexed bus, yet has an output called
Address Strobe (e.g., 680x0 devices), this pin should not
be tied to the output.
/UAS Upper Address Strobe (tri-state output, active Low).
When the IUSC takes control of the bus and operates as a
master, it drives /UAS Low when it places the more signifi-
cant 16 bits of an address on AD15-0. External memory
and other slave devices (or de-multiplexing latches) should
capture the MS address at each rising edge on this line.
R//W Read/Write control (input/tri-state output, Low signi-
fies “write”). R//W and /DS indicate read and write cycles
on the bus, for host processors/buses having this kind of
signalling. When the IUSC has taken control of the bus and
is operating in master mode, this pin is an output that
remains valid throughout the Low time of /DS. In slave
cycles, the IUSC samples R//W at each leading/falling
edge on /DS.
/DS Data Strobe (input/tri-state output, active Low). R//W
and /DS indicate read and write cycles on the bus, for host
processors/buses having this kind of signalling. It is an
output when the IUSC has taken control of the bus and is
operating in master mode, otherwise, it is an input that is
qualified by /CS Low or /INTACK Low. In master mode, the
R//W line remains valid throughout the Low time of this line.
In slave mode, the IUSC samples R//W at each leading/
falling edge on this line. For slave write cycles and master
read cycles, the IUSC captures data at the rising (trailing)
edge on this line. For slave read cycles the IUSC provides
valid data on the AD lines within the specified access time
after this line goes Low , and keeps the data valid until after
the master releases this line to High. For master write
cycles, the IUSC places valid data on the AD lines before
it drives this signal to Low, and keeps the data valid until
after it drives this line back to High.
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PS97USC0200