Z16C32 Datasheet, PDF (47/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Address: 00000
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
Upper//Lower Byte Select (WO)
Address 0 (WO)
Address 1 (WO)
Address 2 (WO)
Address 3 (WO)
Address 4 (WO)
Byte//Word Access (WO)
Channel Load DMA (WO)
0 0 Normal Operation
0 1 Auto Echo
1 0 External Local Loopback
1 1 Internal Local Loopback
Rx/Tx
Mode
Rx/Tx Reset
0 0 0 0 0 Null Command
0 0 0 0 1 Reserved
0 0 0 1 0 Reset Highest IUS
0 0 0 1 1 Reserved
0 0 1 0 0 Trigger Channel Load DMA
0 0 1 0 1 Trigger Rx DMA
0 0 1 1 0 Trigger Tx DMA
0 0 1 1 1 Trigger Rx & Tx DMA
0 1 0 0 0 Reserved
0 1 0 0 1 Rx FIFO Purge
0 1 0 1 0 Tx FIFO Purge
0 1 0 1 1 Rx & Tx FIFO Purge
0 1 1 0 0 Reserved
0 1 1 0 1 Load Rx Character Count
0 1 1 1 0 Load Tx Character Count
0 1 1 1 1 Load Rx & Tx Character Count
1 0 0 0 0 Reserved
1 0 0 0 1 Load TC0
1 0 0 1 0 Load TC1
1 0 0 1 1 Load TC0 & TC1
1 0 1 0 0 Select Serial Data LSB First _*
1 0 1 0 1 Select Serial Data MSB First
1 0 1 1 0 Select Straight Memory Data _*
1 0 1 1 1 Select Swapped Memory Data
1 1 0 0 0 Reserved
1 1 0 0 1 Reserved
1 1 0 1 0 Reserved
1 1 0 1 1 Reserved
1 1 1 0 0 Reserved
1 1 1 0 1 Reserved
1 1 1 1 0 Reserved
1 1 1 1 1 Reserved
Channel
Command
(WO)
* Selected
Upon Reset
Figure 34. Channel Command/Address Register (CCAR)
PS97USC0200
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