Z16C32 Datasheet, PDF (41/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Z16C32 IUSC^™
Base Address
Base Address + 2
Base Address + 4
AD15
Buffer #1
AD<31-24>
AD<15-8>
CNT<15-8>
AD0
AD<23-16>
AD<7-0>
CNT<7-0>
Base Address + 6
Base Address + 8
#2 Base Address
#2 Base Address + 2
#2 Base Address + 4
Base #2
Buffer #2
AD<31-24>
AD<15-8>
AD<31-24>
AD<15-8>
CNT<15-8>
AD<23-16>
AD<7-0>
AD<23-16>
AD<7-0>
CNT<7-0>
#2 Base Address + 6
#2 Base Address + 8
#3 Base Address
#3 Base Address + 2
#3 Base Address + 4
Base #3
Buffer #3
AD<31-24>
AD<15-8>
AD<31-24>
AD<15-8>
CNT<15-8>
AD<23-16>
AD<7-0>
AD<23-16>
AD<7-0>
CNT<7-0>
#n - 1 Base Address + 6
#n - 1 Base Address + 8
#n Base Address
#n Base Address + 2
#n Base Address + 4
Base #n
Buffer #n
AD<31-24>
AD<15-8>
Ignored
Ignored
00000000
AD<23-16>
AD<7-0>
Ignored
Ignored
00000000
Figure 30a. Linked Array-Chained, 16-Bit Bus, Big End Array
Note:
The addition of frame status/control information in the array with Linked Frame
Status Transfer Enabled is similar for Big and Little End Array. See Figure 30b.
PS97USC0200
41