Z16C32 Datasheet, PDF (114/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
AC CHARACTERISTICS (Continued)
Timing Table
No
Symbol
Parameter
Min
Max
103
TsIEI(PIA)
104
ThIEI(PIA)
105
TdPIA(IEO)
106
TdPIA(INT)
IEI to Pulsed /INTACK Fall Setup Time
10
IEI to Pulsed /INTACK Rise Hold Time
0
Pulsed /INTACK Fall to IEO Delay
60
Pulsed /INTACK Fall to /INT Inactive Delay
200
107
TdPIAf(RDY)
Pulsed /INTACK Fall to /RDY Fall Delay
200
108
TdPIAr(RDY)
Pulsed /INTACK Rise to /RDY Rise Delay
40
109
TdPIA(Wf)
Pulsed /INTACK Fall to /WAIT Fall Delay
40
110
TdPIA(Wr)
Pulsed /INTACK Fall to /WAIT Rise Delay
200
111
TdSIA(INT)
112
TwSTBh
113
TwRESl
114
TwRESh
Status /INTACK Fall to IEO Inactive Delay
200
/Strobe High Width
50
/RESET Low Width
170
/RESET High Width
60
115
TdRES(STB)
116
TdDSf(RDY)
117
TdWRf(RDY)
118
TdWRr(RDY)
/RESET Rise to /STB Fall
/DS Fall to /RDY Fall Delay
/WR Fall to /RDY Fall Delay
/WR Rise to /RDY Rise Delay
60
50
50
40
119
120
121a
121b
122a
122b
TdRDf(RDY)
TwCLKl
TwCLKh
TwCLKh
TcCLK
TcCLK
/RD Fall to /RDY Fall Delay
CLK Low Width
CLK High Width
CLK High Width (Linked List Mode)
CLK Cycle Time
CLK Cycle Time (Linked List Mode)
50
25
25
35
50
60
123
TfCLK
CLK Fall Time
124
TrCLK
CLK Rise Time
125
TdCLKr (UAS)
CLK Rise to /UAS Fall Delay
126
TwUASl
/UAS Low Width
5
5
30
25
127
TdCLKf(UAS)
CLK Fall to /UAS Rise Delay
128
TdCLKr(AS)
CLK Rise to /AS Fall Delay
129
TwASl
/AS Low Width
130
TdCLKf(AS)
CLK Fall to /AS Rise Delay
30
30
25
30
131
TdAS(DSr)
132
TdCLKr(DS)
133
TwDSlr
134
TdCLKf(DS)
/AS Rise to /DS Fall (Read) Delay
CLK Rise to /DS Delay
/DS (Read) Low Width
CLK Fall to /DS Delay
25
30
75
30
135
TsDR(DS)
136
ThDR(DS)
137
TdCLK(RW)
138
TdAS(RD)
Read Data to /DS Rise Setup Time
Read Data to /DS Rise Hold Time
CLK Rise to R//W Delay
/AS Rise to /RD Fall Delay
30
0
30
25
139
TdCLKr(RD)
140
TwRDl
141
TdCLKf(RD)
142
TsDR(RD)
CLK Rise to /RD Delay
/RD Low Width
CLK Fall to /RD Delay
Read Data to /RD Rise Setup Time
30
75
30
30
143
ThDR(RD)
144
TdCLK(ADD)
145
TdCLK(AD)
146
ThAD(PC)
Read Data to /RD Rise Hold Time
CLK Rise to Direct Address Delay
CLK Rise to Address Delay
Address to CLK Rise Hold Time
0
30
TdCLKf(DS) 35
0
Z16C32 IUSC^™
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
[2]
[3]
[3]
[12]
[12]
[6]
[6,7,13]
[6]
[6]
[6,7,13]
[6]
[6,8]
[6]
[6,9,13]
[6]
[6]
[6]
[6]
[6,8]
[6]
[6,9]
[6]
[6]
[6]
[1,6]
[6]
[6]
114
PS97USC0200