Z16C32 Datasheet, PDF (52/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Address: 00001
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
0
1
1
0
HDLC
Receiver
Mode
0 0 Disabled
0 1 One Byte, No Control
1 0 One Byte, Plus Control
1 1 Extended, Plus Control
Rx Address
Search Mode
Rx 16-Bit Control
Rx Logical Control Enable
0
1
1
0
HDLC
Transmitter
Mode
Shared Zero Flags
Tx Preamble Enable
0 0 Abort
0 1 Extended Abort
1 0 Flag
1 1 CRC/Flag
Tx
Underrun
Condition
Figure 42. Channel Mode Register, HDLC Mode
Address: 00001
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 1 Transparent Bisync
EBCDIC
Reserved
Receiver
Mode
0 1 1 1 Transparent Bisync
Transmitter
Mode
EBCDIC
Tx Preamble Enable
0 0 SYN
0 1 DLE/SYN
1 0 CRC/SYN
1 1 CRC/DLE/SYN
Tx
Underrun
Condition
Figure 43. Channel Mode Register, Transparent Bisync Mode
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PS97USC0200