Z16C32 Datasheet, PDF (55/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Address: 00010
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
0 0 0 8 Bits
0 0 1 1 Bit
0 1 0 2 Bits
0 1 1 3 Bits
1 0 0 4 Bits
1 0 1 5 Bits
1 1 0 6 Bits
1 1 1 7 Bits
Reserved
HDLC Tx Last
Character Length
Counter By-pass Enable
Loop Sending (RO)
On Loop (RO)
0 0 Both Edges
0 1 Rising Edge Only
1 0 Falling Edge Only
1 1 Adjust/Sync Inhibit
DPLL Adjust/Sync Edge
Clock Missed Latched/Unlatch
2 Clocks Missed Latched/Unlatch
DPLL in Sync/Quick Sync
RCC FIFO Clear (WO)
RCC FIFO Valid (RO)
RCC FIFO Overflow (RO)
Figure 48. Channel Command/Status Register (CCSR)
PS97USC0200
55