Z16C32 Datasheet, PDF (10/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
DMA AND BUS INTERFACE CAPABILITIES
Z16C32 IUSC^™
The IUSC’s two versatile DMA channels combined with a
flexible bus interface gives it the ability to meet a wide
variety of application requirements. The time required to
move data into and out of the transmitter and receiver is
minimized by the IUSC’s speed (20 MHz clock, three clock
cycles per word, typical); two buffer-chaining modes with
linked-frame status transfer; early buffer termination to
keep received frames in separate memory buffers; and
vectored interrupts. Some of the these features are briefly
described below, however, the user should refer to the
IUSC Technical Manual for additional information.
DMA Modes
The IUSC contains two DMA channels, one for the trans-
mitter and one for the receiver. Each channel supports a
32-bit address and a 16-bit byte count. The channels
operate in one of four modes. In normal mode, the proces-
sor must reload the address and length at the end of each
buffer. In Pipelined mode, the processor can load the
address and length of the next buffer at any time during the
DMA transfer to the first buffer. In Array-Chained mode the
processor creates a table of address/length pairs in memory
for automatic transfer by the channel. In Linked List mode
the processor creates a linked list of address and length
pairs in memory to be automatically transferred by the
channel.
Single Buffer Mode is the most basic of the four data
transfer types. The starting address of each memory buffer
and the maximum number of characters to be transferred
to or from memory are programmed into the IUSC regis-
ters. When the DMA is enabled, it transfers all data be-
tween system memory and the transmit and receive FIFOs.
Pipelined Mode is similar to Single Buffer Mode with the
addition of an extra set of registers into which the proces-
sor can load to reload the DMA with the address and count
of the next memory buffer. Therefore, when a buffer is
complete, the IUSC is pre-programmed with the address
and count of the next buffer so the DMA need not stop
between each buffer as long as software stays one step
ahead of memory buffer usage.
In Array Mode, one of the two chaining modes, software
sets up a table of memory buffer information. The length of
the array is only limited by the amount of system memory
available for buffers. The IUSC is programmed with the
location of the array of buffer addresses and sizes. This
mode has the advantage that a burst of short frames is less
likely to overrun the systems ability to keep up. The use of
receive status block and transmit control block along with
the early buffer termination feature simplifies the segmen-
tation and reassembly of serial messages in memory
buffers. When a DMA channel fetches a buffer count of
zero, it stops and can create an End-Of-Array interrupt.
Linked List Mode is the most versatile of DMA modes. It has
the Array Mode’s ability to switch buffers rapidly without
the requirement for the buffer information to be in a continu-
ous table. Each link entry contains: The starting address to
write or read the data; the size of the buffer; optional status
or control information; and a pointer to the next link.
Memory buffers can easily be added and removed from
the list by changing the links in list entries.
DMA Features
In Linked List Mode, the IUSC has a programmable feature
to facilitate the use of buffers in a ring. When this feature is
enabled, the DMA writes a zero back to the buffer length
field of each array or list entry after it is read. Therefore, if
a linked list wraps around on itself, a DMA channel will not
reuse a buffer until software has processed the buffer, and
indicated that its eligible for reuse by writing a nonzero
value in the count field (fetching a count value of zero
deactivates the DMA channel). This feature can also be
used in array mode to track buffer use.
In both Bus Slave and Master Modes, the IUSC can read
and write data words in either byte order. It supports the
Little Endian convention used by many Intel microproces-
sors and the Big Endian convention used by many Motorola
microprocessors. When the IUSC is bus master, it can be
programmed to generate only the upper 16-bit address
when required and, consequently, save a clock cycle on
each transfer (three clocks per transfer instead of four).
When using the IUSC on a 16-bit bus and the starting
address of the message is on an odd address, the IUSC
automatically reorients itself onto even word boundaries
by first fetching a byte. This is especially valuable when
retransmitting a frame with a different size header than was
received. Two pins are available as status signals of the
type of transfer in progress.
There are a variety of command and status registers to
control and monitor the DMA channels. A DMA channel
can be aborted with either the /ABORT pin or by software
command. A pause command is also available to tempo-
rarily suspend transfers.
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PS97USC0200