Z16C32 Datasheet, PDF (28/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
CONTROL REGISTERS (Continued)
Address: 00100 (Shared)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Z16C32 IUSC^™
Tx Channel Array Count (RO)
Rx Channel Array Count (RO)
Reserved
Figure 13a. DMA Array Count Register (DACR)
Getlink (in DCMR)
Channel Array Count 3
Channel Array Count 2
Channel Array Count 1
Channel Array Count 0
0 0 0 0 Array Operation Not Started
0 0 0 1 Fetched Last Byte of Array
0 0 1 0 Fetched Fifth Byte of Array
0 0 1 1 Fetched Fourth Byte of Array
0 1 0 0 Fetched Third Byte of Array
0 1 0 1 Fetched Second Byte of Array
0 1 1 0 Fetched First Byte of Array
0 1 1 1 Fetched Last Byte of Buffer
Array-Chained
000
000
000
000
001
001
001
001
100
100
100
100
101
101
101
101
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Array Operation Not Started
Fetched Last Byte of Array
Fetched Fifth Byte of Array
Fetched Fourth Byte of Array
Fetched Third Byte of Array
Fetched Second Byte of Array
Fetched First Byte of Array
Fetched Last Byte of Linked Address
Invalid
Invalid
Invalid
Invalid
Fetched Third Byte of Linked Address
Fetched Second Byte of Linked Address
Fetched First Byte of Linked Address
Fetched Last Byte of Buffer
Linked Array-Chained
Figure 13b. Channel Array Count Bit Combinations
Note: See the Z16C32 Technical Manual for the appropri-
ate table with Linked Status Transfer feature enabled.
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PS97USC0200