Z16C32 Datasheet, PDF (17/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
Clock Multiplexers
PRELIMINARY
I/O Port
Z16C32 IUSC^™
The clock multiplexer logic selects the receive and trans-
mit clocks and optional outputs on the /RxC and/or /TxC
pin(s). In the Z16C32, the PORT0 and PORT1 pins can be
used directly as receive and transmit clocks, as well as
being used as inputs to the counters.
Time Slot Assigner
The Port pins are general-purpose I/O pins. They are used
as additional modem control lines or other I/O functions.
Each port bit is individually programmable as general-
purpose input, as an output, or for a dedicated input or
output function. This programming is done in the Port
Control Register. Whether used as inputs or outputs, the
port pins can be read at any time.
The IUSC is equipped with two Time Slot Assigners to
support ISDN and Fractional T1 communications. There is
one assigner for the receiver. Each time slot assigner
selects one or more time slots within a frame, however, the
selected time slots must be contiguous. The first selected
time slot is programmable from slot 0 (the first slot) to slot
127 of the frame. The number of concatenated slots is
programmable from 1 to 15 (total slots). The time of the first
slot can be offset an integral number of clocks. This offset
is a delay and is programmable from 0 (no offset) to 7
clocks in increments of one clock (one bit cell). This offset
can be used to compensate for delays in frame sync
detection logic.
The dedicated functions of the port pins include Time Slot
Assigner gate outputs, transmit complete output, clock
inputs, receive sync output, or frame sync input.
The port pins capture edge transitions. Programming for
the capture is done using the Port Latched/Unlatch com-
mand bits in the Port Status Register. Each port bit is
individually controlled. The Latched/Unlatch bit is used as
a status signal to indicate that a transition has occurred on
the port pin and as a command to open the latches that
capture this transition. Both rising edge and falling edge
are detected. When a transition is detected, the latch
closes, holding the post transition state of the input.
Test Modes
The IUSC can be programmed for local loopback or auto
echo operation. In local loopback, the output of the trans-
mitter is internally routed to the input of the receiver. This
allows testing of the IUSC data paths without any external
logic. Auto echo connects the RxD pin directly to the TxD
pin. This is useful for testing serial links external to the
IUSC.
The Latched/Unlatch bit is held at 0 if no transitions occur
on the port pin; this bit is set to a 1 when a rising edge or
falling edge transition is detected, or immediately after the
latch is opened if one or more transitions occurred while
the latch was closed. Writing a 0 to the Latched/Unlatch bit
has no effect on the latch. Writing a 1 to this bit resets the
status bit and opens the latch. To use the port as an input
without edge detection, a 1 would be written to the Latched/
Unlatch bit to open the latch and then the Port Status
Register would be read to obtain the current pin input
status.
PS97USC0200
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