Z16C32 Datasheet, PDF (13/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Z16C32 IUSC^™
Buffer 1 Address
Buffer 1 Length
Buffer 1 RSBR or 0
Buffer 1 RSHR or 0
0
Link Address
of Entry2
Ring Buffer Mode
Writes this word
to 0 after it is read.
Integrated Frame Status
Transfer writes the Receive
Status Block (or 0) here.
Buffer 2 Address
Buffer 2 Length
Buffer 2 RSBR or 0
Buffer 2 RSHR or 0
0
Link Address
of Entry3
Buffer 3 Address
Buffer 3 Length
Buffer 3 RSBR or 0
Buffer 3 RSHR or 0
0
Link Address
of Entry1
Figure 4. Linked List Mode with Linked Frame Status Transfer and Ring Buffer Features
Another method by which the DMA and serial channel
work together is using the Transmit Character Counter to
break a large block of data into a number of fixed length
frames. For example, it is desired to transmit a large file
which is located in several memory buffers as fixed length
smaller frames. With the IUSC, the serial channel is pro-
grammed to send the end-of-frame sequence each time
the set number of bytes is transmitted. Therefore, DMA
transfers are not interrupted, nor is system response
required to break the large file into frames.
The IUSC provides higher throughput than discrete serial
and DMA chip solutions because discrete chips do not
directly communicate with each other and, therefore, the
status of one device must be read by the CPU and
communicated to the other. This typically requires inter-
rupts and the suspension of activity until status/control
information is updated. This uses precious time and bus
bandwidth, which can limit total throughput.
PS97USC0200
13