Z16C32 Datasheet, PDF (11/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
Bus Interface & Utilization
PRELIMINARY
Interrupts
Z16C32 IUSC^™
The bus interface module stands between the external bus
pins and an on-chip 16-bit data bus that interconnects the
other functional modules. It includes several flexible bus
interfacing options that are controlled by the contents of
the Bus Configuration Register (BCR). The BCR is auto-
matically the destination of the first write to the IUSC by the
host processor after a reset.
The IUSC is compatible with both multiplexed and non-
multiplexed bus interfaces and can transfer either 8 or 16
bits. It supports data transfers with /RD and /WR or R//W
and /DS strobe pins and either format of byte ordering. The
IUSC generates the Wait or Ready acknowledge hand-
shaking used by Intel or Motorola microprocessors. Also,
three styles of interrupt acknowledge signals are sup-
ported for automated return of an interrupt vector to any
common microprocessor.
There are several options that control how the IUSC uses
the bus. The /BIN and /BOUT pins are available to form a
bus-grant daisy chain. The IUSC has several options on
how it arbitrates requests for bus mastership between
channels and how long it stays off the bus between
requests. The priority of the two DMA channels is program-
mable and can alternate between requests to allow both
channels equal access to the bus. Once one of the
channels has mastership of the bus, control can be passed
to the other channel if it is requesting or the IUSC can be
forced off the bus. A programmable preempt feature
selects whether the higher priority channel can take over
control of the bus if it starts requesting control while the
lower priority channel is using the bus.
The IUSC maximizes the use of its 32-byte FIFOs by
holding /BUSREQ active until the transmit FIFO is full, the
receive FIFO is empty, or both. The programmable dwell
timers can be used to limit how long the IUSC holds bus
mastership by counting either bus transfers, clock cycles
or both. Therefore, the combination of programmable FIFO
request levels, channel arbitration options, and program-
mable dwell timer features provide application software
the flexibility to optimize the IUSCs bus occupancy to meet
system throughput and bus response requirements.
The interrupt subsystem of the IUSC derives from Zilog’s
experience in providing the most advanced interrupt ca-
pabilities in the microprocessor field. These capabilities
are at their best when used with a Zilog microprocessor,
but it is easy to interface the IUSC to work well with other
microprocessors as well. Four pins are dedicated to create
an interrupt daisy-chain hierarchy within the Serial Chan-
nel and between the Serial Channel and the DMA.
When an IUSC responds to an interrupt acknowledge from
the CPU, it places an interrupt vector on the data bus. To
speed interrupt response time, the IUSC modifies three
bits in the vector to indicate which type of interrupt is being
requested. Separate vectors are provided for the serial
channel and DMA to easily discriminate the interrupt
source.
The DMA has four interrupt sources each for the receive
and transmit channels. Each interrupt source is indepen-
dently enabled and there is a master enable for all DMA
interrupts. The four interrupt sources are End Of Array/ End
of Link, End Of Buffer, Hardware Abort, and Software
Abort.
Each of the six types of interrupts in the serial portion IUSC
(Receive Status, Receive Data, Transmit Status, Transmit
Data, I/O Status and Device Status) has three bits associ-
ated with it: Interrupt Pending (IP), Interrupt-Under-Ser-
vice (IUS) and Interrupt Enable (IE). If the IE bit for a given
source is set, then that bit can source request interrupts.
Note that individual sources within the six types also have
their own interrupt arm bits. Finally, there is a Master
Interrupt Enable (MIE) bit which globally enables or dis-
ables all interrupts from the serial channel.
The Interrupt (/INT), Interrupt Acknowledge (/INTACK),
Interrupt Enable In (IEI) and Interrupt Enable Out (IEO)
pins are provided to create an automated mechanism to
place the vector on the bus among the highest priority
pending interrupts from multiple devices. The device with
the highest pending interrupt (/INT Low, IEI High) places a
vector on the bus in response to an interrupt acknowledge
cycle.
In the IUSC, the IP bit signals that an interrupt is pending.
If an IUS bit is set, this interrupt is being serviced and all
interrupt sources of lower priority are prevented from
requesting interrupts. An IUS bit is set during an interrupt
acknowledge cycle if there are no higher priority devices
requesting interrupts.
PS97USC0200
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