Z16C32 Datasheet, PDF (18/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PROGRAMMING
PRELIMINARY
Z16C32 IUSC^™
An Electronic Programmer’s Manual (MS DOS based) and
a Technical Manual are available to provide details about
programming the IUSC. Also included are explanations
and features of all registers in the IUSC.
The registers in the IUSC are programmed by the system
to configure the channel. Before this can occur, the system
must set up the bus interface by writing to the Bus Configu-
ration Register (BCR). The BCR has no specific address
and is only accessible after a hardware reset of the device.
The first write to the IUSC, after a hardware reset, programs
the BCR. From that time on other channel registers can be
accessed. No specific address need be presented to the
IUSC for the BCR write; the IUSC knows that the first write
after a hardware reset is destined for the BCR.
In the multiplexed bus case, all registers are directly
addressable through the address latched by /AS at the
beginning of each bus cycle. The D//C pin is still used to
directly access the receive and send data registers (RDR
and TDR) with a multiplexed bus; if D//C is High, the
address latched by /AS is ignored and an access of RDR
or TDR is performed.
In the non-multiplexed bus case, the channel registers are
accessed indirectly using the address pointer in the Chan-
nel Command/Address Register (CCAR). The address of
the desired register is first written to the CCAR and then the
selected register is accessed; the pointer in the CCAR is
automatically cleared after this access.
Two more points about the IUSC should be noted here.
Channel Reset bit in the CCAR places the channel in the
reset state. To exit this reset state either a word of all zeros
is written to the CCAR (16-bit bus) or a byte of all zeros is
written to the lower byte of the CCAR (8-bit bus). Secondly,
after reset, the transmit and receive clocks are disabled.
The first thing that should be done in any initialization
sequence is a write to the Clock Mode Control Register
(CMCR) to select a clock source for the receiver and
transmitter.
The Serial/DMA (S//D) pin is used to differentiate between
the serial channel and the DMA registers. The DMA regis-
ters fall into three logic groupings; common registers that
apply to both transmit and receive, transmit registers, and
receive registers. The registers for DMA transmit functions
and receive functions are symmetric and therefore, a
single diagram is shown for each in the following pages.
When addressing the DMA registers, the Data/Control (D/
/C) pin selects between the transmit and receive registers.
For example, there is a DMA byte count register for
transmit and receive (TBCR and RBCR) at address 10101
with S//D pin Low. The TBCR is selected with the D//C pin
Low, and the RBCR is selected with the D//C pin High. The
format of these two registers is shown in Figure 20.
The register addressing is shown in Table 2 and the table
assumes that the BCR register bit 0 is set to 1. The A5-A1
column in the Table reflects the state of AD5-AD1, AD13-
AD9, CCAR5-CCAR1 or DCAR5-DCAR1 as applicable.
The bit assignments of the registers are shown in Figures
7 through 80. See the IUSC Technical Manual for details.
The register addressing is shown in Table 2 and the bit
assignments for the registers are shown in Figure 6.
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PS97USC0200