Z16C32 Datasheet, PDF (45/121 Pages) Zilog, Inc. – IUSC™ INTEGRATED UNIVERSAL SERIAL CONTROLLER

ZILOG
PRELIMINARY
Z16C32 IUSC^™
Base Address
Base Address + 1
Base Address + 2
Base Address + 3
Base Address + 4
Base Address + 5
Base Address + 6
Base Address + 7
Base Address + 8
Base Address + 9
Base Address + 10
Base Address + 11
Buffer #1
AD7
AD0
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
CNT<15-8>
CNT<7-0>
RSB/TCB <15-8>
RSB/TCB <7-0>
RCHR/TCLR <15-8>
RCHR/TCLR <7-0>
0
0
Base Address + 12
Base Address + 13
Base Address + 14
Base Address + 15
Base #2
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
#2 Base Address
#2 Base Address + 1
#2 Base Address + 2
#2 Base Address + 3
#2 Base Address + 4
#2 Base Address + 5
#2 Base Address + 6
#2 Base Address + 7
#2 Base Address + 8
#2 Base Address + 9
#2 Base Address + 10
#2 Base Address + 11
Buffer #2
AD<31-24>
AD<23-16>
AD<15-8>
AD<7-0>
CNT<15-8>
CNT<7-0>
RSB/TCB <15-8>
RSB/TCB <7-0>
RCHR/TCLR <15-8>
RCHR/TCLR <7-0>
0
0
Figure 32b. Linked Frame Status Transfer Enables
PS97USC0200
45