M16C62_M Datasheet, PDF (96/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

DMAC
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) The priorities of channels and DMA transfer timing
If a DMA transfer request signal falls on a single sampling cycle (a sampling cycle means one period from
the leading edge to the trailing edge of BCLK), the DMA request bits of applicable channels concurrently
turn to “1”. If the channels are active at that moment, DMA0 is given a high priority to start data transfer.
When DMA0 finishes data transfer, it gives the bus right to the CPU. When the CPU finishes single bus
access, then DMA1 starts data transfer and gives the bus right to the CPU.
An example in which DMA transfer is carried out in minimum cycles at the time when DMA transfer
request signals due to external factors concurrently occur.
Figure 1.13.6 An example of DMA transfer effected by external factors.
An example in which DMA transmission is carried out in minimum
cycles at the time when DMA transmission request signals due to
external factors concurrently occur.
BCLK
DMA0
DMA1
CPU
INT0
DMA0
request bit
INT1
DMA1
request bit
Figure 1.13.6. An example of DMA transfer effected by external factors
Obtainment
of the bus
right
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