M16C62_M Datasheet, PDF (467/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

DMAC
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.9.3 Operation of DMAC (repeated transfer mode)
In repeat transfer mode, choose functions from the items shown in Table 2.9.2. Operations of the circled
items are described below. Figure 2.9.6 shows an example of operation and Figure 2.9.7 shows the set-
up procedure.
Table 2.9.2. Choosed functions
Item
Set-up
Transfer space
Fixed address from an arbitrary 1 M bytes space
O Arbitrary 1 M bytes space from a fixed address
Fixed address from fixed address
Unit of transfer
8 bits
O 16 bits
Operation (1) When software trigger is selected, setting software DMA request bit to “1” generates a DMA
transfer request signal.
(2) If DMAC is active, data transfer starts, and the contents of the address indicated by the DMAi
forward-direction address pointer are transferred to the address indicated by the DMAi desti-
nation pointer. When data transfer starts directly after DMAC becomes active, the value of
the DMAi transfer counter reload register is reloaded to the DMAi transfer counter, and the
value of the DMAi source pointer is reloaded by the DMAi forward-direction address pointer.
Each time a DMA transfer request signal is generated, 2 byte of data is transferred. The
DMAi transfer counter is down counted, and the DMAi forward-direction address pointer is up
counted.
(3) Though DMAi transfer counter is underflowed, DMA enable bit is still “1”. The DMA interrupt
request bit changes to “1” simultaneously.
(4) After DMAi transfer counter is underflowed, when the next DMA request is generated, DMA
transfer is repeated from (1).
BCLK
Address bus
(1) Request signal for a DMA transfer occurs
(2) Data transfer begins
(3) Underflow
CPU use
Destination
Source
Dummy cycle
CPU use
Destination
Source
Dummy cycle
CPU use
RD signal
WR signal
Data bus
Write signal to
software DMAi
request bit
DMAi
request bit
DMA transfer
counter
CPU use
Destination
Source
Dummy cycle
CPU use
Destination
Source
Dummy cycle
CPU use
0116
Indeterminate
0016
FF16
DMAi
interrupt
request bit
Cleared to “0” when interrupt request is accepted, or cleared by software
DMAi
“1”
enable bit
• In the case in which the number of transfer times is set to 2.
Figure 2.9.6. Example of operation of repeated transfer mode
Destination
Source
Dummy cycle
CPU use
Destination
Source
Dummy cycle
CPU use
0116
0016
2-150