M16C62_M Datasheet, PDF (492/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Power Control
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) Clearing stop mode and wait mode
The stop mode and wait mode can be cleared by generating an interrupt request, or by resetting
hardware. Set the priority level of the interrupt to be used for clearing, higher than the processor
interrupt priority level (IPL), set that of the interrupt to “0” not to be used for clearing, and enable the
interrupt enable flag (I flag). When an interrupt clears a mode, that interrupt is processed. Table
2.15.1 shows the interrupts that can be used for clearing a stop mode and wait mode.
(4) BCLK in returning from wait mode or stop mode
(a) Returning from wait mode
The processor immediately returns to the BCLK, which was in use before entering wait mode.
(b) Returning from stop mode
CM06 is set to “1” when the device enters stop mode after selecting the main clock for BCLK. CM17,
CM16, and CM07 do not change state. In this case, when restored from stop mode, the device starts
operating in divided-by-8 mode.
When the device enters stop mode after selecting the subclock for BCLK, CM06, CM17, CM16, and
CM07 all do not change state. In this case, when restored from stop mode, the device starts operat-
ing in low-speed mode.
Table 2.15.1. Interrupts available for clearing stop mode and wait mode
Interrupt for clearing
Bus collision detection interrupt
DMA0 interrupt
DMA1 interrupt
Key input interrupt
A-D interrupt
UART0 transmit interrupt
UART0 receive interrupt
UART1 transmit interrupt
UART1 receive interrupt
UART2 transmit interrupt
UART2 receive interrupt
SI/O3 interrupt
SI/O4 interrupt
Timer A0 interrupt
Timer A1 interrupt
Timer A2 interrupt
Timer A3 interrupt
Timer A4 interrupt
Timer B0 interrupt
Timer B1 interrupt
Timer B2 interrupt
Timer B3 interrupt
Timer B4 interrupt
Timer B5 interrupt
INT0 interrupt
INT1 interrupt
INT2 interrupt
INT3 interrupt
INT4 interrupt
INT5 interrupt
NMI interrupt
Wait mode
CM02 = 0
Possible
Impossible
Impossible
Possible
Note 3
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Possible
CM02 =1(Note 6),
CM07 = 0, CM05 = 0
Note 1
Impossible
Impossible
Possible
Impossible
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 4
Note 4
Note 2, Note 5
Note 2, Note 5
Note 2, Note 5
Note 2, Note 5
Note 2, Note 5
Note 2, Note 5
Note 2, Note 5
Note 2, Note 5
Note 2, Note 5
Note 2, Note 5
Note 2, Note 5
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Stop mode
Note 1
Impossible
Impossible
Possible
Impossible
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 4
Note 4
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Possible
Possible
Possible
Possible
Possible
Possible
Possible
Note 1: Can be used when an external clock is selected (UART0, UART1).
Can be used when an external clock in clock synchronous serial I/O mode is selected (UART2).
Note 2: Can be used when the external signal is being counted in event counter mode.
Note 3: Can be used in one-shot mode and one-shot sweep mode.
Note 4: Can be used when an external clock is selected.
Note 5: Can be used when count source is fC32.
Note 6: When the MCU running in low-speed or low power dissipation mode, do not enter wait mode
with CM02 is set to “1”.
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