M16C62_M Datasheet, PDF (475/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Address Match Interrupt
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.12 Address Match Interrupt Usage
2.12.1 Overview of the address match interrupt usage
The address match interrupt is used for correcting a ROM or for a simplified debugging-purpose monitor.
The following is an overview of the address match interrupt usage.
(1) Enabling/disabling the address match interrupt
The address match interrupt enable bit can be used to enable and disable an address match interrupt.
It is affected neither by the processor interrupt priority level (IPL) nor the interrupt enable flag (I flag).
(2) Timing of the address match interrupt
An interrupt occurs immediately before executing the instruction in the address indicated by the ad-
dress match interrupt register. Set the first address of the instruction in the address match interrupt
register. Setting a half address of an instruction or an address of tabulated data does not generate an
address match interrupt.
The first instruction of an interrupt routine does not generate an address match interrupt either.
(3) Returning from an address match interrupt
The address put in the stack when an address match interrupt occurs depends on the instruction not
yet executed (the instruction the address match interrupt register indicates). The return address is not
put in the stack. For this reason, to return from an address match interrupt, either rewrite the content
of the stack and use the REIT instruction or use the POP instruction to restore the stack to the state as
it was before the interrupt occurred and return by use of a jump instruction.
Figure 2.12.1 shows unexecuted instructions and corresponding the stacked addresses.
<Instructions whose address is added to by 2 when an address match interrupt occurs>
• 16-bit operation code instructions
• 8-bit operation code instructions given below
ADD.B:S #IMM8,dest
SUB.B:S #IMM8,dest
AND.B:S
OR.B:S #IMM8,dest
MOV.B:S #IMM8,dest
STZ.B:S
STNZ.B:S #IMM8,dest
STZX.B:S #IMM81,#IMM82,dest
CMP.B:S #IMM8,dest
PUSHM src
POPM
JMPS
#IMM8
JSRS
#IMM8
MOV.B:S #IMM,dest (However, dest = A0/A1)
#IMM8,dest
#IMM8,dest
dest
<Instructions whose address is added to by 1 when an address match interrupt occurs>
• Instructions other than those listed above
Figure 2.12.1. Unexecuted instructions and corresponding stacked addresses
(4) How to determine an address match interrupt
Address match interrupts can be set at two different locations. However, both location will have the
same vector address. Therefore, it is necessary to determine which interrupt has occurred; address
match interrupt 0 or address match interrupt 1. Using the content of the stack, etc., determine which
interrupt has occurred according to the first part of the address match interrupt routine.
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