M16C62_M Datasheet, PDF (435/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

A-D Converter
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7.3 Operation of A-D Converter (in one-shot mode, an external trigger selected)
In one-shot mode, choose functions from those listed in Table 2.7.3. Operations of the circled items are
described below. Figure 2.7.7 shows timing chart, and Figure 2.7.8 shows the set-up procedure.
Table 2.7.3. Choosed functions
Item
Set-up
Operation clock
φAD
O
Divided-by-4 fAD / divided-
by-2 fAD / fAD
Resolution
Analog input pin
Trigger for starting
A-D conversion
O 8-bit / 10-bit
O One of AN0 pin to AN7 pin
Software trigger
O Trigger by ADTRG
Item
Expanded analog
input pin
Sample & Hold
Set-up
O Not used
Either ANEX0 pin or
ANEX1 pin
External operation amplifier
connection mode
Not activated
O Activated
___________
Operation (1) If the level of the ADTRG changes from “H” to “L” with the A-D conversion start flag set to “1”,
the A-D converter begins operating.
(2) After A-D conversion is completed, the content of the successive comparison register (con-
version result) is transmitted to A-D register i. At this time, the A-D conversion interrupt re-
quest bit goes to “1”. Also the A-D converter stops operating.
___________
(3) If the level of the ADTRG pin changes from “H” to “L”, the A-D converter carries out conversion
___________
from step (1) again. If the level of the ADTRG pin changes from “H” to “L” while conversion is
in progress, the A-D converter stops the A-D conversion in process, and carries out conver-
sion from step (1) again.
(1) Start A-D conversion
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
(2) A-D conversion is
complete
(3) Start A-D
conversion
φAD
A-D
conversion
“1”
start flag
“0”
“H”
ADTRG
“L”
A-D register i
A-D conversion ^{“1”}
interrupt request _{“0”}
Set to “1” by software
Result
Cleared to “0” when interrupt request is accepted, or cleared by software
Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.7.7. Operation timing of one-shot mode, with an external trigger selected
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