M16C62_M Datasheet, PDF (219/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Timing (Vcc = 3V)
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 3V
Memory Expansion Mode and Microprocessor Mode
(When accessing external memory area with wait, and select multiplexed bus)
Read timing
BCLK
CSi
ADi
/DBi
ADi
BHE
ALE
RD
td(BCLK–CS)
tcyc
60ns.max
td(AD–ALE) (tcyc/2–45)ns.min
Address
tdz(RD–AD)
8ns.max
th(ALE–AD)
50ns.min
tac3(RD–DB)
td(BCLK–AD)
60ns.max
td(AD–RD)
0ns.min
th(RD–CS)
(tcyc/2)ns.min
th(BCLK–CS)
4ns.min
Data input
Address
th(RD–DB)
tSU(DB–RD) ^0ns.min
80ns.min
th(BCLK–AD)
4ns.min
td(BCLK–ALE)
60ns.max
th(BCLK–ALE)
–4ns.min
td(BCLK–RD)
60ns.max
th(RD–AD)
(tcyc/2)ns.min
th(BCLK–RD)
0ns.min
Write timing
BCLK
CSi
td(BCLK–CS)
60ns.max
ADi
/DBi
ADi
BHE
ALE
Address
td(AD–ALE)
(tcyc/2–60)ns.min
td(BCLK–AD)
60ns.max
td(BCLK–ALE) _{th(BCLK–ALE)}
60ns.max
–4ns.min
WR,WRL,
WRH
tcyc
th(WR–CS)
(tcyc/2)ns.min
td(BCLK–DB)
80ns.max
Data output
th(BCLK–CS)
4ns.min
th(BCLK–DB)
4ns.min
Address
td(DB–WR)
(tcyc*3/2–80)ns.min
th(WR–DB)
(tcyc/2)ns.min
th(BCLK–AD)
4ns.min
td(AD–WR)
0ns.min
td(BCLK–WR)
60ns.max
th(WR–AD)
(tcyc/2)ns.min
th(BCLK–WR)
0ns.min
Measuring conditions :
• VCC=3V
• Input timing voltage : Determined with VIL=0.48V,VIH=1.5V
• Output timing voltage : Determined with VOL=1.5V,VOH=1.5V
Figure 1.23.12. VCC = 3V timing diagram (5)
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