M16C62_M Datasheet, PDF (379/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Clock-Synchronous Serial I/O
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Setting UARTi transmit/receive mode register (i=0 to 2)
b7
b0 _{UART0 transmit/receive mode register}
b7
0
0 0 0 1 U0MR [Address 03A016]
0
UART1 transmit/receive mode register
U1MR [Address 03A816]
Must be fixed to “001”
Internal/external clock select bit
0 : Internal clock
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Sleep select bit
Must always be “0” in clock synchronous I/O mode
b0 _{UART2 transmit/receive mode register}
0 0 0 1 _{U2MR [Address 037816]}
Must be fixed to “001”
Internal/external clock select bit
0 : Internal clock
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
Invalid in clock synchronous I/O mode
TXD, RXD I/O polarity reverse bit
Usually set to “0”
Setting UARTi transmit/receive control register 0 (i=0 to 2)
b7
b0 _{UART0 transmit/receive control register 0}
00
0
0
U0C0 [Address 03A416]
UART1 transmit/receive control register 0
U1C0 [Address 03AC16]
BRG count source select bit
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Must not be set
CTS/RTS function select bit
(Valid when bit 4 = “0”)
0 : CTS function is selected (Note)
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
Data output select bit
0 : TxDi pin is CMOS output
1 : TxDi pin is N-channel open-drain output
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
Transfer format select bit
0 : LSB first
b7
b0 _{UART2 transmit/receive control register 0}
00
0
0
U2C0 [Address 037C16]
BRG count source select bit
b1 b0
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Must not be set
CTS/RTS function select bit
(Valid when bit 4 = “0”)
0 : CTS function is selected (Note)
Transmit register empty flag
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register
(transmission completed)
CTS/RTS disable bit
0 : CTS/RTS function enabled
CLK polarity select bit
0 : Transmission data is output at falling edge
of transfer clock and reception data is input
at rising edge
Transfer format select bit
0 : LSB first
Note: Set the corresponding port direction register to “0” .
Setting UART transmit/receive control register 2 and UART2 transmit/receive control register 1
b7
00
b0 _{UART transmit/receive control register 2}
0 0 _{UCON [Address 03B016]}
UART0 transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
UART1 transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
Valid when bit 5 = “1”
CLK/CLKS select bit 1
0 : Normal mode (CLK output is CLK1 only)
Reserved bit
Must always be set to “0”
b7
00
b0 _{UART2 transmit/receive control register 1}
U2C1 [Address 037D16]
UART2 transmit interrupt cause select bit
0 : Transmit buffer empty (Tl = 1)
Data logic select bit
0 : No reverse
Error signal output enable bit
Must always be “0” in clock synchronous I/O mode
Continued to the next page
Figure 2.4.8. Set-up procedure of transmission in clock-synchronous serial I/O mode (1)
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