M16C62_M Datasheet, PDF (485/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Multiple Interrupts
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Interrupt Enable Flag (I flag)
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting
this flag to “1” enables all maskable interrupts; setting it to “0” disables all maskable interrupts. This
flag is set to “0” after reset.
The content is changed when the I flag is changed causes the acceptance of the interrupt request in
the following timing:
• When changing the I flag using the REIT instruction, the acceptance of the interrupt takes
effect as the REIT instruction is executed.
• When changing the I flag using one of the FCLR, FSET, POPC, and LDC instructions, the
acceptance of the interrupt is effective as the next instruction is executed.
When changed by REIT instruction
Interrupt request generated
Determination whether or not to
accept interrupt request
Time
Previous
instruction
REIT
Interrupt sequence
(If I flag is changed from 0 to 1 by REIT instruction)
When changed by FCLR, FSET, POPC, or LDC instruction
Interrupt request generated
Determination whether or not to
accept interrupt request
Time
Previous
instruction
FSET I
Next instruction
Interrupt sequence
(If I flag is changed from 0 to 1 by FSET instruction)
Figure 2.14.3. The timing of reflecting the change in the I flag to the interrupt
(3) Interrupt Request Bit
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is
accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware.
The interrupt request bit can also be set to "0" by software. (Do not set this bit to "1").
(4) Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Set the interrupt priority level using the interrupt priority level select bit, which is one of the component
bits of the interrupt control register. When an interrupt request occurs, the interrupt priority level is
compared with the IPL. The interrupt is enabled only when the priority level of the interrupt is higher
than the IPL. Therefore, setting the interrupt priority level to “0” disables the interrupt.
Table 2.14.1 shows the settings of interrupt priority levels and Table 2.14.2 shows the interrupt levels
enabled, according to the contents of the IPL.
The following are conditions under which an interrupt is accepted:
· interrupt enable flag (I flag) = 1
· interrupt request bit = 1
· interrupt priority level > IPL
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