M16C62_M Datasheet, PDF (461/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

DMAC
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.9 DMAC Usage
2.9.1 Overview of the DMAC usage
DMAC transfers one data item held in the source address to the destination address every time a transfer
request is generated. The following is an overview of the DMAC usage.
(1) Source address and destination address
Both the register which indicates a source and the register which indicates a destination comprise of
24 bits, so that each can cover a 1M bytes space. After transfer of one bit of data is completed, the
address in either the source register or the destination register can be incremented. However, both
registers cannot be incremented. The links between the source and destination are as follows:
(a) A fixed address from an arbitrary 1M bytes space
(b) An arbitrary 1M bytes space from a fixed address
(c) A fixed address from another fixed address
(2) The number of bits of data transferred
The number of bit of data indicated by the transfer counter is transferred. If a 16-bit transfer is se-
lected, up to 128K bytes can be transferred. If an 8-bit transfer is selected, up to 64K bytes can be
transferred. The transfer counter is decremented each time one bit of data is transferred, and a DMA
interrupt request occurs when the transfer counter underflows.
(3) DMA transfer factor
________
The DMA transfer factor can be selected from the following 25 factors: falling edge/two edges of INT0/
________
INT1 pin, timer A0 interrupt request through timer A4 interrupt request, timer B0 interrupt request
through timer B5 interrupt request, UART0 transmission interrupt request, UART0 reception interrupt
request, UART1 transmission/UART1 reception interrupt request, UART2 transmission interrupt re-
quest, UART2 reception interrupt request, SI/O 3, 4 interrupt request, A-D conversion interrupt re-
quest, and software trigger.
When software trigger is selected, DMA transfer is generated by writing “1” to software DMA interrupt
request bit. When other factor is selected, DMA transfer is generated by generating corresponding
interrupt request.
(4) Channel priority
If DMA0 transfer request and DMA1 transfer request occur simultaneously, priority is given to DMA0.
(5) Writing to a register
When writing to the source register or the destination register with DMA enabled, the content of the
register with a fixed address will change at the time of writing. Therefore, the user should not write to
a register with a fixed address when the DMA enable bit is set to “1”. The contents of the register with
‘forward direction’ selected, and the transfer counter, are changed when reloaded. A reload occurs
either when the transfer counter underflows, or when the DMA enable bit is re-enabled, after having
been disabled.
The reload register can be written to, as in normal conditions.
(6) Reading to a register
The reload register can be read to, as in normal conditions.
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