M16C62_M Datasheet, PDF (381/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Clock-Synchronous Serial I/O
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.4.3 Operation of the Serial I/O (transmission in clock-synchronous serial I/O
mode, transfer clock output from multiple pins function selected)
In transmitting data in clock-synchronous serial I/O mode, choose functions from those listed in Table
2.4.2. Operations of the circled items are described below. Figure 2.4.10 shows the operation timing, and
Figures 2.4.11 and 2.4.12 show the set-up procedures.
Table 2.4.2. Choosed functions
Item
Set-up
Item
Set-up
Transfer clock
source
CTS function
CLK polarity
Transfer clock
O Internal clock (f1 / f8 / f32)
External clock (CLKi pin)
Transmission
interrupt factor
Transmission buffer empty
O _{Transmission complete}
CTS function enabled
O CTS function disabled
Output transfer clock
Not selected
to multiple pins
(Note 1)
O Selected
Output transmission data at
O the falling edge of the
transfer clock
Output transmission data at
the rising edge of the
transfer clock
O LSB first
Data logic select
function
(Note 2)
TXD, RXD I/O
polarity reverse bit
(Note 2)
O No reverse
Reverse
O No reverse
Reverse
MSB first
Note 1: This can be selected only when UART1 is used in combination with the internal clock. When this function is
_______ _______
_______ _______
selected, UART1 CTS/RTS function can not be utilized. Set the UART1 CTS/RTS disable bit to “1”.
Note 2: UART2 only.
Operation (1) Setting the transmit enable bit to “1” makes data transmissible status ready.
(2) When transmission data is written to the UART1 transmit buffer register, transmission data
held in the UART1 transmit buffer register is transmitted to the UART1 transmit register in
synchronization with the first falling edge of the transfer clock. At this time, the first bit of the
transmission data is transmitted from the TxD1 pin. Then the data is transmitted bit by bit
from the lower order in synchronization with the falling edges of the transfer clock.
(3) When transmission of 1-byte data is completed, the transmit register empty flag goes to “1”,
which indicates that the transmission is completed. The transfer clock stops at “H” level. At
this time, the UART1 transmit interrupt request bit goes to “1”.
(4) Setting CLK/CLKS select bit 1 to “1” and setting CLK/CLKS select bit 0 to “1” causes the
CLKS1 pin to go to the transfer clock output pin. Change the transfer clock output pin when
transmission is halted.
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