M16C62_M Datasheet, PDF (240/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

CPU Rewrite Mode (Flash Memory Version)
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Figure 1.26.2 shows a flowchart for setting/releasing the CPU rewrite mode. Figure 1.26.3 shows a flow-
chart for shifting to the low speed mode. Always perform operation as indicated in these flowcharts.
Flash memory control register 0
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
FMR0
Address
03B716
When reset
XX0000012
Bit symbol
Bit name
FMR00 RY/BY status flag
Function
0: Busy (being written or erased)
1: Ready
RR WW
FMR01
FMR02
FMR03
CPU rewrite mode
select bit (Note 1)
Lock bit disable
select bit (Note 2)
Flash memory reset bit
(Note 3)
0: Normal mode
(Software commands invalid)
1: CPU rewrite mode
(Software commands acceptable)
0: Block lock by lock bit data is
enabled
1: Block lock by lock bit data is
disabled
0: Normal operation
1: Reset
Reserved bit
Must always be set to “0”
FMR05
User ROM area select bit ( _{0: Boot ROM area is accessed}
Note 4) (Effective in only _{1: User ROM area is accessed}
boot mode)
Nothing is assigned.
When write, set "0". When read, values are indeterminate.
Note 1: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. Write to
this bit only when executing out of an area other than the internal flash memory. Also
only when NMI pin is “H” level. Clear this bit to “0” after read array command.
Note 2: For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in succession
when the CPU rewrite mode select bit = “1”. When it is not this procedure, it is not
enacted in “1”. This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.
Note 3: Effective only when the CPU rewrite mode select bit = 1. Set this bit to 0 subsequently
after setting it to 1 (reset).
Note 4: Write to this bit only when executing out of an area other than the internal flash memory.
Flash memory control register 1
b7 b6 b5 b4 b3 b2 b1 b0
0000
000
Symbol
FMR1
Address
03B616
When reset
XXXX0XXX2
Bit symbol
Reserved bit
Bit name
Function
Must always be set to “0”
RR WW
FMR13 Flash memory power
supply-OFF bit (Note)
Reserved bit
0: Flash memory power supply is
connected
1: Flash memory power supply-off
Must always be set to “0”
Note :
For this bit to be set to “1”, the user needs to write a “0” and then a “1” to it in
succession. When it is not this procedure, it is not enacted in “1”. This is necessary to
ensure that no interrupt or DMA transfer will be executed during the interval. During
parallel I/O mode,programming,erase or read of flash memory is not controlled by this
bit,only by external pins. Write to this bit only when executing out of an area other than
the internal flash memory.
Figure 1.26.1. Flash memory control registers
1-221