M16C62_M Datasheet, PDF (201/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Timing (Vcc = 5V)
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = – 20^oC to 85^oC / – 40^oC to
85^oC (Note 3), CM15 = “1” unless otherwise specified)
Table 1.23.21. Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
Symbol
Parameter
Measuring condition ^Standard
Min. Max.
td(BCLK-AD)
th(BCLK-AD)
Address output delay time
Address output hold time (BCLK standard)
25
4
th(RD-AD)
Address output hold time (RD standard)
0
th(WR-AD)
Address output hold time (WR standard)
0
td(BCLK-CS)
th(BCLK-CS)
Chip select output delay time
Chip select output hold time (BCLK standard)
25
4
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
25
Figure 1.23.1 _{– 4}
25
th(BCLK-RD)
td(BCLK-WR)
RD signal output hold time
WR signal output delay time
0
25
th(BCLK-WR)
td(BCLK-DB)
WR signal output hold time
Data output delay time (BCLK standard)
0
40
th(BCLK-DB)
td(DB-WR)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
4
(Note1)
th(WR-DB)
Data output hold time (WR standard)(Note2)
0
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) =
10 ⁹
f(BCLK) ^{– 40 [ns]}
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
Hold time of data bus is expressed in
t = –CR X ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
Note 3: Specify a product of -40°C to 85°C to use it.
R
DBi
C
1-182