M16C62_M Datasheet, PDF (445/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

A-D Converter
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.7.8 Operation of A-D Converter (in repeat sweep mode 0)
In repeat sweep 0 mode, choose functions from those listed in Table 2.7.8. Operations of the circled items
are described below. Figure 2.7.17 shows timing chart, and Figure 2.7.18 shows the set-up procedure.
Table 2.7.8. Choosed functions
Item
Set-up
Item
Operation clock AD
O
Divided-by-4 fAD / divided-
by-2 fAD / fAD
Trigger for starting
A-D conversion
Resolution
Analog input pin
O 8-bit / 10-bit
Expanded analog
input pin
AN0 and AN1 (2 pins) / AN0
O to AN3 (4 pins) / AN0 to AN5
(6 pins) / AN0 to AN7 (8 pins) Sample & Hold
Set-up
O Software trigger
Trigger by ADTRG
O Not used
External ope-amp
connection mode
Not activated
O Activated
Operation (1) Setting the A-D conversion start flag to “1” causes the A-D converter to start the conversion
on voltage input to the AN0 pin.
(2) After the A-D conversion of voltage input to the AN0 pin is completed, the content of the
successive comparison register (conversion result) is transmitted to A-D register 0.
(3) The A-D converter converts all pins selected by the user. The conversion result is transmitted
to A-D register i corresponding to each pin every time A-D conversion on the pin is com-
pleted. The A-D conversion interrupt request bit does not go to “1”.
(4) The A-D converter continues operating until the A-D conversion start flag is set to “0” by
software.
(1) Start A-D conversion
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
(2) AN1 conversion begins after AN0
conversion is complete
(3) Consecutive conversion
8-bit resolution : 28 φAD cycles
10-bit resolution : 33 φAD cycles
(4) A-D conversion
is complete
φAD
A-D
conversion
“1”
start flag
“0”
A-D register 0
Set to “1” by software.
Result
Cleared to “0” by software
A-D register 1
Result
A-D register i
Result
Note: When φAD frequency is less than 1MHZ, sample and hold function cannot be selected.
Conversion rate per analog input pin is 49 φAD cycles for 8-bit resolution and 59 φAD cycles for 10-bit resolution.
Figure 2.7.17. Operation timing of repeat sweep 0 mode
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