M16C62_M Datasheet, PDF (305/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Timing
Mitsubishi microcomputers
M16C / 62M Group
(Low voltage version)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = – 20^oC to 85^oC / – 40^oC to
85^oC (Note 3), CM15 = “1” unless otherwise specified)
Table 1.31.21. Memory expansion and microprocessor modes (with no wait)
Symbol
Parameter
Measuring condition
td(BCLK-AD) Address output delay time
th(BCLK-AD) Address output hold time (BCLK standard)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip select output delay time
Chip select output hold time (BCLK standard)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
Figure 1.31.1
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
WR signal output delay time
WR signal output hold time
Data output delay time (BCLK standard)
Data output hold time (BCLK standard)
td(DB-WR)
th(WR-DB)
Data output delay time (WR standard)
Data output hold time (WR standard)(Note2)
Note 1: Calculated according to the BCLK frequency as follows:
Standard
Min. Max.
60
4
0
0
60
4
60
–4
60
0
60
0
80
4
(Note1)
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10 ⁹
td(DB – WR) =
– 80
f(BCLK) X 2
[ns]
Note 2: This is standard value shows the timing when the output is off,
and doesn't show hold time of data bus.
Hold time of data bus is different by capacitor volume and pull-up
(pull-down) resistance value.
R
Hold time of data bus is expressed in
DBi
t = –CR X ln (1 – VOL / VCC)
C
by a circuit of the right figure.
For example, when VOL = 0.2VCC, C = 30pF, R = 1kΩ, hold time
of output “L” level is
t = – 30pF X 1kΩ X ln (1 – 0.2VCC / VCC)
= 6.7ns.
Note 3: Specify a product of –40°C to 85°C to use it.
P0
P1
P2
30pF
P3
P4
P5
P6
P7
P8
P9
P10
Figure 1.31.1. Port P0 to P10 measurement circuit
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