M16C62_M Datasheet, PDF (401/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

UART
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
2.5.2 Operation of Serial I/O (transmission in UART mode)
In transmitting data in UART mode, choose functions from those listed in Table 2.5.4. Operations of the
circled items are described below. Figure 2.5.8 shows the operation timing, and Figures 2.5.9 and 2.5.10
show the set-up procedures.
Table 2.5.4. Choosed functions
Item
Set-up
Transfer clock
source
(Note 1)
O Internal clock (f1 / f8 / f32)
External clock (CLKi pin)
CTS function
O CTS function enabled
CTS function disabled
Transmission
interrupt factor
O Transmission buffer empty
Transmission complete
Note 1: UART0, UART1 only.
Note 2: UART2 only.
Item
Sleep mode
(Note 1)
Data logic select
function
(Note 2)
TXD, RXD I/O
polarity reverse bit
(Note 2)
Bus collision
detection function
(Note 2)
Set-up
O Sleep mode off
Sleep mode selected
O No reverse
Reverse
O No reverse
Reverse
O Not selected
Selected
Operation (1) Setting the transmit enable bit to “1” and writing transmission data to the UARTi transmit
buffer register readies the data transmissible status.
________
________
(2) When input to the CTSi pin goes to “L”, transmission starts (the CTSi pin needs to be con-
trolled on the reception side).
(3) Transmission data held in the UARTi transmit buffer register is transmitted to the UARTi
transmit register. At this time, the first bit (the start bit) of the transmission data is transmitted
from the TxDi pin. Then, data is transmitted, bit by bit, in sequence: LSB, ····, MSB, parity bit,
and stop bit(s).
(4) When the stop bit(s) is (are) transmitted, the transmit register empty flag goes to “1”, which
indicates that transmission is completed. At this time, the UARTi transmit interrupt request bit
goes to “1”. The transfer clock stops at “H” level.
(5) If the transmission condition of the next data is ready when transmission is completed, a start
bit is generated following to stop bit(s), and the next data is transmitted.
2-84