M16C62_M Datasheet, PDF (542/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

External Buses
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Chip select control register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CSR
Address
000816
When reset
0116
Bit symbol
CS0
CS1
CS2
CS3
CS0W
CS1W
CS2W
CS3W
Bit name
CS0 output enable bit
CS1 output enable bit
CS2 output enable bit
CS3 output enable bit
CS0 wait bit
CS1 wait bit
CS2 wait bit
CS3 wait bit
Function
RW
0 : Chip select output disabled
(Normal port pin)
1 : Chip select output enabled
0 : Wait state inserted
1 : No wait state
Figure 4.2.3. Chip select control register
4.2.3 Bus Types
The M16C/62A Group has two types of buses: a separate bus where separate pins are used for address
output and data input/output and a multiplexed bus where pins are time- multiplexed and switched be-
tween address output and data input/output to save the number of pins used.
A separate bus is used to access devices such as ROM and RAM which have separate buses. The areas
accessed via separate buses can be allocated for programs and data.
A multiplexed bus is used to access devices such as ASSPs which have multiplexed buses. The areas
accessed via a multiplexed bus can only be allocated for data. Programs cannot be located in these areas.
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The area accessed via a multiplex bus can be selected from three types of area CS2 area, CS1 area, and
entire space by setting the multiplexed bus select bits (bits 4 and 5) of the processor mode register 0 (address
000416). However, the entire space cannot be selected when operating in the microprocessor mode.
Areas not accessed via multiplexed bus are accessed through separate buses.
When accessing an area set for access via a multiplexed bus the BYTE pin is “H” level, the data bus D0
to D7 is multiplexed with address bus A0 to A7.
If the BYTE pin is “L” level, the data bus D0 to D7 is multiplexed with address bus A1 to A8. In either case,
the bus is switched between data and address separated only in time.
In the latter case, however, the addresses of connected devices are mapped into even addresses (every
other addresses) of the M16C/62A. Therefore, be sure to access the M16C/62A's even addresses in
length of bytes when accessing a connected device.
4.2.4 R/W Modes
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The read/write signal that is output when accessing an external area can be selected between the RD/
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BHE/WR and the RD/WRH/WRL modes by setting the R/W mode select bit (bit 2) of the processor mode
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_____ _________
register 0 (address 000416). Use the RD/BHE/WR mode to access a 16-bit wide RAM and the RD/WRH/
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WRL mode to access an 8-bit wide RAM.
_____ ________ ______
When the M16C/62A is reset, the RD/BHE/WR mode is selected by default. To switch over the R/W
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mode, change the RD/BHE/WR to the RD/WRH/WRL mode before accessing an external RAM.
_____ ________ ______
_____ _________ ________
Refer to the connection examples of RD/BHE/WR and RD/WRH/WRL shown in Section 4.3, "Connection
Examples."
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