M16C62_M Datasheet, PDF (202/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Timing (Vcc = 5V)
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
VCC = 5V
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = – 20^oC to 85^oC / – 40^oC to
85^oC (Note 2), CM15 = “1” unless otherwise specified)
Table 1.23.22. Memory expansion mode and microprocessor mode
(with wait, accessing external memory, multiplex bus area selected)
Symbol
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
Parameter
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Measuring condition
Standard
Min. Max.
25
4
(Note1)
(Note1)
Unit
ns
ns
ns
ns
td(BCLK-CS) Chip select output delay time
25
ns
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
Chip select output hold time (BCLK standard)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
4
ns
(Note1)
ns
(Note1)
ns
td(BCLK-RD) RD signal output delay time
25
ns
th(BCLK-RD) RD signal output hold time
td(BCLK-WR) WR signal output delay time
Figure 1.23.1 ⁰
ns
25
ns
th(BCLK-WR) WR signal output hold time
td(BCLK-DB) Data output delay time (BCLK standard)
0
ns
40
ns
th(BCLK-DB)
td(DB-WR)
Data output hold time (BCLK standard)
Data output delay time (WR standard)
4
ns
(Note1)
ns
th(WR-DB) Data output hold time (WR standard)
(Note1)
ns
td(BCLK-ALE) ALE signal output delay time (BCLK standard)
25
ns
th(BCLK-ALE) ALE signal output hold time (BCLK standard)
td(AD-ALE) ALE signal output delay time (Address standard)
–4
ns
(Note1)
ns
th(ALE-AD)
td(AD-RD)
ALE signal output hold time (Adderss standard)
Post-address RD signal output delay time
td(AD-WR)
tdZ(RD-AD)
Post-address WR signal output delay time
Address output floating start time
Note 1: Calculated according to the BCLK frequency as follows:
30
ns
0
ns
0
ns
8
ns
10 ⁹
th(RD – AD) =
f(BCLK) X 2
[ns]
10 ⁹
th(WR – AD) =
f(BCLK) X 2
[ns]
10 ⁹
th(RD – CS) =
f(BCLK) X 2
[ns]
10 ⁹
th(WR – CS) =
f(BCLK) X 2
[ns]
td(DB – WR) =
10 ^{9 X 3}
f(BCLK) X 2 ^{– 40} [ns]
10 ⁹
th(WR – DB) =
f(BCLK) X 2
[ns]
10 ⁹
td(AD – ALE) = _{f(BCLK) X 2 – 25 [ns]}
Note 2: Specify a product of -40°C to 85°C to use it.
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