M16C62_M Datasheet, PDF (36/615 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Reset
Mitsubishi microcomputers
M16C / 62A Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(1) Processor mode register 0 (Note 1)
(000416)···
0016
(2) Processor mode register 1
(000516)··· 0 0 0 0 0
0
(3) System clock control register 0
(000616)··· 0 1 0 0 1 0 0 0
(4) System clock control register 1
(000716)··· 0 0 1 0 0 0 0 0
(5) Chip select control register
(000816)··· 0 0 0 0 0 0 0 1
(6) Address match interrupt enable register (000916)···
00
(7) Protect register
(000A16)···
000
(8) Watchdog timer control register
(000F16)··· 0 0 0 ? ? ? ? ?
(9) _{Address match interrupt register 0}
(001016)···
0016
(001116)···
0016
(001216)···
00 0 0
(10)Address match interrupt register 1
(001416)···
0016
(001516)···
0016
(001616)···
00 0 0
(11)DMA0 control register
(12)DMA1 _{control register}
(13) _{INT3 interrupt control register}
(002C16)··· 0 0 0 0 0 ? 0 0
(003C16)··· 0 0 0 0 0 ? 0 0
(004416)···
0 0 ? 00 0
(14)Timer B5 interrupt control register
(004516)···
?000
(15)Timer _{B4 interrupt control register}
(16)Timer B3 interrupt control register
(004616)···
(004716)···
?000
?0 0 0
(17)SI/O4 interrupt control register
(004816)···
00 ? 0 0 0
(18)SI/O3 _{interrupt control register}
(19)Bus ^{collision detection interrupt}
control register
(20) DMA0 interrupt control register
(004916)···
(004A16)···
(004B16)···
0 0 ?0 0 0
?0 0 0
?0 0 0
(21) DMA1 interrupt control register
(004C16)···
?0 0 0
(22) Key input interrupt control register
(004D16)···
?0 0 0
(23)A-D conversion interrupt control register _{(004E16)···}
?0 0 0
(24)UART2 transmit interrupt control register _{(004F16)···}
?0 0 0
(25) UART2 receive interrupt control register (005016)···
?0 0 0
(26)UART0 transmit interrupt control register _{(005116)···}
(27)UART0 receive interrupt control register _{(005216)···}
(28)UART1 transmit interrupt control register _{(005316)···}
?000
?000
?000
(29) UART1 receive interrupt control register
(30) _{Timer A0 interrupt control register}
(31) _{Timer A1 interrupt control register}
(32) _{Timer A2 interrupt control register}
(33) _{Timer A3 interrupt control register}
(34) _{Timer A4 interrupt control register}
(35) _{Timer B0 interrupt control register}
(36) _{Timer B1 interrupt control register}
(37) _{Timer B2 interrupt control register}
(38) _{INT0 interrupt control register}
(39) _{INT1 interrupt control register}
(40) _{INT2 interrupt control register}
(41) _{Timer B3,4,5 count start flag}
(42)Three-phase _{PWM control register 0}
(43)Three-phase PWM control register 1
(44) Three-phase output buffer register 0
(005416)···
?000
(005516)···
?000
(005616)···
?000
(005716)···
?000
(005816)···
?000
(005916)···
?000
(005A16)···
?000
(005B16)···
?000
(005C16)···
?000
(005D16)···
00?000
(005E16)···
00?000
(005F16)···
00?000
(034016)··· 0 0 0
(034816)···
0016
(034916)···
0016
(034A16)···
0016
(45) Three-phase output buffer register 1
(46)Timer B3 mode register
(47) _{Timer B4 mode register}
(48) Timer B5 mode register
(49)Interrupt cause select register
(50) SI/O3 control register
(51) SI/O4 control register
(034B16)···
0016
(035B16)··· _{0 0 ? 0 0 0 0}
(035C16)··· 0 0 ? 0 0 0 0
(035D16)··· _{0 0 ? 0 0 0 0}
(035F16)···
0016
(036216)···
4016
(036616)···
4016
(52) UART2 special mode register 3 (Note 2) (037516)···
?
(53) UART2 special mode register 2
(037616)···
0016
(54) UART2 special mode register
(037716)···
0016
(55) UART2 transmit/receive mode register
(037816)···
0016
(56)UART2 transmit/receive control register 0 (037C16)··· 0 0 0 0 1 0 0 0
(57)UART2 transmit/receive control register 1 (037D16)··· 0 0 0 0 0 0 1 0
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values must therefore be set.
Note 1: When the VCC level is applied to the CNVSS pin, it is 0316 at a reset.
Note 2: “0016” is read out when set bit 7 (SDDS) of the UART2 special mode register ( address 037716) to “1”.
Figure 1.5.3. Device's internal status after a reset is cleared
1-17